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CD1865 Datasheet(PDF) 96 Page - Intel Corporation |
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CD1865 Datasheet(HTML) 96 Page - Intel Corporation |
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96 / 150 page  CD1865 — Intelligent Eight-Channel Communications Controller 96 Datasheet Even though not all of the CD1865 registers are intended to be read/write, there is no hardware mechanism to prevent the user from writing to them. The registers should, in some cases, not be written to by the host. See the individual register descriptions for details. In the register map, the binary addresses are shown relative to the CD1865 address lines. In 16- and 32-bit systems, it is a common practice to connect 8-bit peripherals to only 1-byte lane. In 16-bit systems, the CD1865 appears at every other address, that is, A0 in the CD1865 is connected to A1 in the host. In 32-bit systems, the CD1865 appears at every fourth address, that is, A0 in the CD1865 is connected to A2 in the host. In both of these cases, the addresses used by a programmer are different than what is shown. For instance, in a 16-bit Motorola 68000-based system (or other ‘big-endian’ processors), the CD1865 is placed on data lines D0–D7 that are at odd addresses in the Motorola manner of addressing. The A0 in the CD1865 is connected to A1 of the 68000. Thus, the CD1865 address $40 becomes $81 to a programmer. It is ‘left-shifted’ one bit, and A0 must be ‘1’ for low-byte (D0–D7) accesses. In a 16-bit Intel system (or other ‘little-endian’ processors), the CD1865 is again placed on data lines D0–D7, but these are at even addresses. The A0 in the CD1865 is connected to the A1 in the host, but the host’s A0 must be a ‘0’ to access data lines D0–D7. Many 32-bit processors have internal logic to ‘steer’ the data to the correct pins regardless of address value. However, if the processor employed does not, a scheme similar to the one described for 16-bit machines can be used, except that the CD1865 addresses are shifted 2 bits instead of one. Table 9. Register Summary (Sheet 1 of 2) Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Global Registers GFRCR Firmware Revision Code SRCR PkgTyp RegAckEn DaisyEn GlobPri UnFair Reserved AutoPri PriSel PPRH Binary Value PPRL Binary Value MSMR Binary Value TSMR Binary Value RSMR Binary Value GSVR User Defined User Defined User Defined User Defined User Defined IT2 IT1 IT0 SRSR ILV[1] ILV[0] RREQext RREQint TREQext TREQint MREQext MREQint MRAR Modified Interrupt Vector Provided On Read TRAR Modified Interrupt Vector Provided On Read RRAR Modified Interrupt Vector Provided On Read GSCR1 User Defined User Defined User Defined C2 C1 C0 User Defined User Defined GSCR2 User Defined User Defined User Defined C2 C1 C0 User Defined User Defined GSCR3 User Defined User Defined User Defined C2 C1 C0 User Defined User Defined CAR Reserved Reserved Reserved Reserved A7(0) C2 C1 C0 |
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