CD1865 datasheet(62/150 Pages) INTEL

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CD1865 — Intelligent Eight-Channel Communications Controller

Datasheet

Regardless of the number or type of exceptions occurring, they are reported to the host one

character at a time; that is, the number-of-bytes value in the Receive Data Count register is not

meaningful. Since every error is reported individually, there is no Receive Time-out Exception

generated if the only characters in the FIFOs are error or exception characters.

7.1.7

Types of Errors

There are four types of errors recognized by the CD1865: parity, framing, line break, and overrun.

If parity checking is enabled, parity errors are logged in the Status FIFO and the suspect data is

placed in the Receive Data FIFO. An error is also logged for framing, that is, absence of a Stop bit.

In these cases, the suspect character is in the Receive Data FIFO and the appropriate status byte is

placed in the Status FIFO.

When a line-break condition is recognized (zero data with zero parity, and no Stop bit), one NULL

(00) character is loaded into the Receive FIFO, and a break status is recorded in the Status FIFO.

Note that if odd parity is set and the bits received are all zeroes, it is marked as both a break

character and a parity error. Generally when a break character is received, pre-set parity error can

be ignored. No further FIFO entries are made until normal-character reception is resumed, for

example, a Start bit is found. The line must go high and then back to low for this to occur.

Multiple errors in 1 byte are possible because the CD1865 evaluates the characters bit-by-bit as it

receives them. For example, a parity error is detected and flagged before the CD1865 recognizes

that a framing error has occurred. Parity plus framing or parity plus break error can occur, but

framing plus a break error cannot occur because, if a character is received with every bit equal to a

‘0’, it is marked as a break character. If some bits are a ‘1’, but the Stop bit is missing, for example,

a ‘0’, it is marked as a framing error. Thus, any one character cannot have both framing and break

errors.

The length of the Stop bit is not checked by CD1865. Any Stop bit long enough to be sampled in

mid-bit time as a ‘1’ is interpreted as a valid Stop bit. In addition to all of the other errors, if an

overrun occurs, the Overrun Error bit is set along with other error bits.

7.1.8

Types of Exceptions

7.1.8.1

Special Character Recognition

‘Special Character Recognition’ is a feature found only on the CD1865 and other Intel data

communications controllers. The on-chip processor compares every good character received with

user-defined special characters stored in registers on the device. Both single-character and two-

character sequence recognition is possible. This capability has several applications, including In-

Band Flow Control. Special-character matches are reported to the host by a Receive Exception

Service Request.

Four Special Character registers are provided per channel, allowing received characters to be

compared to as many as four special characters. However, these four registers are shared between

Receive Special Character Detection and the Send Special Character Command, so some planning

is required for using these characters.

The full set of features and options available as part of Special Character Recognition allows for

Xon/Xoff flow-control to be implemented transparently to the host, and at the same time, detect

either of two other special characters in the data stream and alert the host of their arrival.

CD1865 Datasheet(PDF) 62 Page - Intel Corporation

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