CD1865 datasheet(84/150 Pages) INTEL

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CD1865 — Intelligent Eight-Channel Communications Controller

Datasheet

Off-Limit Registers

The CD1865 communicates to the host by shared access to its on-device RAM. Of the 128-byte

locations in the CD1865 address range, only 41 locations are defined as registers available to the

host. The rest are used by the CD1865 for internal variable storage. Users should not access these

registers since it can cause the CD1865 to malfunction.

8.2

Access Duty Cycle

The host access to the CD1865 appears to be a simple static read or write cycle, but the actual

access occurs by arbitrating for the local (on-device) bus and ‘stealing’ one-bus cycle. This is

completely hidden from the user in normal circumstances, and successive accesses to the CD1865

may be done ‘back-to-back’ with no delay. However, if the host were to repetitively read from (or

write to) the CD1865 as fast as possible over many cycles, enough CD1865 internal bus cycles

would be ‘stolen’ that the CD1865 processor might not be able to keep pace with its processing.

This situation could only occur if the host was continuously testing a bit while waiting for it to

change state. If there is a requirement to do something similar, insert a delay in the host code so that

the net-duty cycle of accesses is less than ten percent. This limitation applies only when the

CD1865 is sending and receiving data on one or more channels. When initializing or re-

configuring a channel, these registers can be written to at a fast pace.

8.3

Accessing FIFOs Versus Other Registers

The FIFO storage array is under the control of the CD1865 at all times. This is necessary to ensure

that the FIFO is available for the CD1865 processor to access whenever needed. During normal

operation, the CD1865 processor sets the FIFO pointers to the value required to transfer data,

regardless of the value placed in the Channel Access register (CAR) by the user. Therefore, the

user cannot access the FIFOs in this manner.

FIFOs can only be accessed in the context of an active Service Request. At this time only the

CD1865 processor causes the FIFO pointers to be set to the appropriate value for the channel being

serviced. FIFOs are then accessed by the Indirect Indexed registers.

8.4

Initialization

The CD1865 initialization begins with a mandatory hardware reset applied through the active-low

RESET* Input. The system Clock (CLK) Input must be active during the hardware reset, and the

reset duration must be at least five clock periods. It is not necessary to synchronize RESET* Input

with CLK. Refer to Figure 28.

Immediately following the hardware reset, the CD1865 goes through a firmware initialization,

reaching an Idle mode within 500

µs. This can be verified by the host by reading the Global

Service Vector register and finding its contents to be FF Hex. Upon internal reset completion, the

user can then configure the CD1865 for the required channel functions.

A software reset can be performed by setting certain bits in the Channel Command register (CCR).

Setting bits 7 and 0 to a ‘1’ resets all channels. This is done by forcing the CD1865 processor to

jump to the same power-up sequence that it uses upon hardware reset. Whether the reset is caused

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