CD1865 datasheet(6/150 Pages) INTEL

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CD1865 — Intelligent Eight-Channel Communications Controller

Datasheet

10.5.2 Unclocked Bus Interface ...................................................................... 136

11.0

Package Specifications ....................................................................................... 145

12.0

Ordering Information ............................................................................................ 146

Index

....................................................................................................................................... 147

Figures

Functional Block Diagram ..................................................................................... 9

Internal Block Diagram ........................................................................................ 22

Foreground/Background Internal Structure ......................................................... 24

Internal Operation Flow Chart ............................................................................. 25

Internal Service Acknowledge Decision Tree...................................................... 30

Internal Fair-Share Operation ............................................................................. 31

Receive Timer Operation .................................................................................... 34

Three-Level Interrupt with Three-Level Acknowledge Example.......................... 38

Three-Level Interrupt with Single-Level Acknowledge Example ......................... 39

Single-Level Interrupt with Single-Level Acknowledge Example ........................ 40

Simple Software Polled Interface Example ......................................................... 41

Polled Code Sequence ....................................................................................... 42

Interrupt Code Sequence .................................................................................... 43

Internal Block Diagram ........................................................................................ 46

2¥ Clock Option................................................................................................... 47

............................................................................................................................ 48

Typical Unclocked Bus Interface ......................................................................... 53

Typical Clocked Bus Interface............................................................................. 54

Incorrect VME Interface ...................................................................................... 56

Correct VME Interface......................................................................................... 57

Bit Synchronization in CD1865 ........................................................................... 58

Receive Operation .............................................................................................. 59

No New Data Timer Logic ................................................................................... 67

Transmitter Operation ......................................................................................... 69

Receiver Flow-Control Logic ............................................................................... 73

Transmitter Flow-Control Logic ........................................................................... 76

Local and Remote Loopback Logic..................................................................... 82

Initialization ......................................................................................................... 85

Clocked Bus Interface Reset............................................................................. 130

Clocked Bus Interface Clocks ........................................................................... 131

Clocked Bus Interface Read Cycle,

Motorola‚-Style Handshake ............................................................................... 131

Clocked Bus Interface Service Acknowledgment Cycle,

Motorola‚-Style Handshake ............................................................................... 132

Clocked Bus Interface Write Cycle,

Motorola‚-Style Handshake ............................................................................... 133

Clocked Bus Interface Read Cycle,

Intel‚-Style Handshake ...................................................................................... 134

Clocked Bus Interface Service Acknowledgment Cycle,

Intel‚-Style Handshake ...................................................................................... 135

Clocked Bus Interface Write Cycle, Intel‚-Style Handshake.............................. 136

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