CD1865 datasheet(23/150 Pages) INTEL

23 / 150 page

Intelligent Eight-Channel Communications Controller — CD1865

Datasheet

The CD1865 workload can be divided into two categories:

• Bit-to-character conversion (and vice versa) — the ‘traditional’ UART function

• Character-level processing such as flow control, FIFO management, and host interface

functions

The CD1865 internal processor handles all these tasks in firmware. A foreground/background

scheme is used: foreground for internal bit-engine interrupts and background for everything else.

This internal structure represented in Figure 3 on page 24, shows how the foreground

communicates with the background. Foreground code handles bit-to-character assembly for

receive, and character-to-bit disassembly for transmit. In either case a Holding register, together

with a Full/Empty bit, acts as the ‘gateway’ between the interrupt-driven foreground and the

polling-loop background code.

The background code executes the polling loop as shown in Figure 4. After power-on reset, the

software runs continuously in an inner and an outer loop. Lower-priority tasks are handled in the

outer loop, and higher-priority tasks are handled in the inner loop. The highest-priority tasks are bit

events that are handled by foreground (that is, interrupt-driven) code.

The inner loop executes eight times as often as the outer loop. It checks each channel’s Full/Empty

bits to sense if another character needs to be moved. It first checks receive, and if there is a

character to be moved, it is moved and execution moves on to the next channel. If receive data does

not need processing, then transmit is checked. This mechanism gives a slightly higher priority to

receive than to transmit, and is favorable because missing a receive character is a fatal error and

being late in transmitting one is not an error. (The effect of this can be observed by programming

the CD1865 for higher-than-rated serial baud rates and providing a source of receive traffic with

virtually 100-percent loading. As the CD1865 is heavily loaded, it leaves short gaps between

transmit characters because the firmware is following the ‘receive’ path through the code. Refer to

Section 6.2.5 for details on maximum performance and maximum line speed).

After eight passes through the inner loop (for example, checking all eight channels for data), one

pass is made through the outer loop. This pass checks one channel for host commands (such as

‘Send Special Character’), timer functions, and a condition that requires posting an external service

request (for example, Receive FIFO full, Transmit FIFO empty, modem signal change, and so on).

If required, the firmware posts the service request within the queue of the appropriate service-

request logic. It then continues normal operation, until the host responds to the service request.

After a single pass through the outer loop, eight passes through the inner loop are again made.

In most cases the CD1865 checks the appropriate bit in RAM to determine which options are

enabled and then modifies its processing accordingly. Some control bits must be interpreted and

moved by the CD1865 firmware from their location in Option Bit registers to other locations in the

device. Therefore, the host must notify the CD1865 when these bits are modified. Then, the

CD1865 alters the channel as commanded. For details on channel command functions, refer to

Section 7.2.

CD1865 Datasheet(PDF) 23 Page - Intel Corporation