CD1865 datasheet(11/150 Pages) INTEL

11 / 150 page

Intelligent Eight-Channel Communications Controller — CD1865

Datasheet

Because the CD1865 RISC processor is processing every character sent or received, features such

as automatic flow control and special character recognition are easily implemented. This further

reduces the processing burden on the host system. Both In-Band (Xon, Xoff) and Out-of-Band

(RTS/CTS, DTR) Flow-Control modes are supported. For in-band flow control, the CD1865

automatically starts and stops its transmitter when the remote unit sends flow-control characters.

The CD1865 also makes it easy for the local host to flow-control the remote, by the ‘send special

character’ commands. For out-of-band flow control, the transmitter optionally asserts RTS and

monitor CTS for permission to send; and assert/negate DTR when the Receive FIFO reaches a

user- definable threshold. Together, the in-band and out-of-band features not only allow the data

flow to be controlled in real time with minimum or no host intervention, it also prevents loss of

data.

As shown on the previous page, the CD1865 can interface virtually any CPU, with a minimum of

glue logic. Refer to the CD1865 Data Sheet for detailed information on how to interface various

microprocessors. Systems with multiple CD1865s are easily implemented, with no external glue,

by device a daisy-chain scheme. A ‘fair share’ feature ensures equal access for all service requests,

both within one CD1865 and across multiple devices.

FIFO — 24 bytes of FIFO are dedicated to each channel partitioned as 8 bytes for transmitter,

8 bytes for receiver, and 8 bytes for status. The receive FIFO has a user-programmable threshold to

optimize system response and latency. The receive FIFO threshold programming range is from 1–8

characters.

Vectored Interrupt Structure — Three interrupt signals ([R, T, M]REQ*) are used. These signals

may also be read as an on-device register. Each REQ* signal represents one of three interrupt

groups: receive, transmit, and modem signal state changes. Upon servicing by the host, an interrupt

vector is generated by the CD1865 to define the interrupt group to be serviced and which CD1865

generated the interrupt. This allows the host software to enter directly into the proper interrupt

service routine, reducing the amount of interaction between the host and the controller, and

determining the nature of the interrupt.

Good Data Interrupt — If data received is all good, the host is advised of the number of good

data bytes in the FIFO, allowing the host to read data without further status queries until all good

data has been transferred.

Fair-Share Interrupt Scheme — To ensure equal service of all channels, a fair share scheme is

used for each interrupt group. No channel can interrupt for the same condition until all others have

a chance to be serviced for the same interrupt condition.

Typical CD1865 Host CPU Interface

CD1865 in Daisy-Chain Scheme

ADDRESS

DATA

CS*

DS*

R/W

DTACK*

ACKIN*

RREQ*

TREQ*

MREQ*

CD1865

CPU

INTERRUPT

CONTROLLER

ADDRESS

DECODE

AND

LOGIC

TxD

RxD

DTR*

DSR*

RTS*

CTS*

CD*

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

Channel 0

CD1865

INTERRUPT

CONTROLLER

CPU

ACKIN* ACKOUT*

CONTROL

CD1865 Datasheet(PDF) 11 Page - Intel Corporation

CD1865 Datasheet(HTML) 11 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL