CD1865 datasheet(54/150 Pages) INTEL

54 / 150 page

CD1865 — Intelligent Eight-Channel Communications Controller

Datasheet

6.4

Interface Examples

There are some general design considerations when interfacing the CD1865 to any host

environment.

The three Service Request pins (*, *, and *) can change at any time, and this can introduce

metastability problems if the interrupt controller requires clocked signals. When designing, take

care that all signals are stable when needed.

The Service Request pin of the type being acknowledged is negated at the end of the service

acknowledgment bus cycle. Often, during the course of servicing one channel, another channel

reaches a state where a request would assert, for example, while servicing receive on channel one,

channel two’s FIFO fills. The Service Request bits in the Service Request Status register (SRSR)

does not reassert until approximately two clock periods after the host completes its write to the End

Of register (). In polled or mixed-mode systems, to determine whether another service request of

the same level is pending, and to make sure that the host does not re-read the SRSR too quickly,

insert a No-Operation (or similar) instruction.

Performing an ‘invalid’ service acknowledgment bus cycle on the CD1865 is permissible, but it

can cause problems in certain circumstances. An Invalid Service Acknowledgment is an

acknowledgment for which there is no request pending.

If a service request acknowledgment bus cycle is performed by the host when no service request is

pending, either of two things can occur. If the value on the address bus matches one of the three

values in the three Service Match registers (), and daisy chaining is enabled, the CD1865 assumes

that another device down the daisy chain should receive the request, and asserts its ACKOUT* pin.

This propagates down the CD1865 chain until eventually the last CD1865 asserts its ACKOUT*.

Figure 18. Typical Clocked Bus Interface

NEW CYCLE MAY BEGIN

DON’T CARE

VALID

DON’T CARE

CD1864

DS*

CS*

R/W*

ADDRESS

UNDEFINED

VALID

DATA-READ

DTACK*

CLOCK

CD1865 Datasheet(PDF) 54 Page - Intel Corporation