CD1865 datasheet(59/150 Pages) INTEL

59 / 150 page

Intelligent Eight-Channel Communications Controller — CD1865

Datasheet

An overrun condition occurs when the new data arrives, but the Receive FIFO and the Receive

Holding register are both full. The new data is lost and the overrun indication is flagged on the

character in the Holding register. That character and its status including the overrun indication is

eventually transferred to the host by a Receive Exception Service Request. Note that this character

is good, and is the last character received before the overrun occurred.

Receiver Service Requests are enabled or disabled by the Receive Data bit in the Enable register

(). Receive Data bit, when set to a ‘1’, enables service requests to be asserted for the above causes.

The Prescaler Period Counter is a 16-bit counter clocked by the system clock. If the system clock is

a 33-MHz clock, the maximum count establishes a clock tick every 1.9859 ms. The Prescaler

Period should be set to generate a minimum tick period of 1.0 ms. The Receive Time-out Counter

is an 8-bit counter decremental on every tick of the Prescaler Period Counter. At the maximum

count per tick, the maximum time-out period is 0.506 seconds.

The Receive Time-out is always enabled to transfer data when the Receive Data Service Request is

enabled. From the system applications view-point, this time-out function is important for

asynchronous data transmission. This is especially true when a FIFO is in use and a service request

threshold for the FIFO is set greater than one character. The Timer Service Request eliminates long

response times when excessive delay between characters occurs caused either by the remote

operator or due to the line being disabled. The ‘No New Data’ Timer Service request, which occurs

after all data is transferred to the host, may be used to manage transfers from the host’s receive data

buffers.

Figure 22. Receive Operation

RECEIVER SHIFT REGISTER

RECEIVER HOLDING REGISTER

FULL/

EMPTY

BIT

RECEIVER

RECEIVE DATA COUNT REGISTER

BACKGROUND CODE:

H.R.-TO-FIFO TRANSFER, FLOW

CONTROL, OTHER FEATURES

FOREGROUND CODE:

BIT ASSEMBLY,

S.R.-TO-H.R. TRANSFER

(INTERRUPT-DRIVEN)

(POLLING LOOP)

DTR

OUT

DSR

RECEIVE

STATUS

FIFO

RECEIVER

FIFO

CD1865 Datasheet(PDF) 59 Page - Intel Corporation

CD1865 Datasheet(HTML) 59 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL