DA6021 datasheet(31/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

31 of 224

www.dialog-semiconductor.com

once the VSYS increases and reaches the 2.375V, point C. In this case the digital core will no longer be in a

reset condition and can read the OTP content.

In this case the device again in G3 is waiting for the VSYS to become valid, VSYS > VSYSREF = 3.0. DA6021

will go then to SOC_G3 state waiting for wakeup condition to be met. In order to have valid VSYS de-bouncing

of 100ms will be needed. The monitor of the system voltage will be done via ADC once the system is in SOC_S0

state or active state.

VSYS voltage and events generated:

Figure 5: VSYS Areas

Event Trigger

Conditions (all

mandatory)

Next state

Note

Main Battery Insertion

VSYS > VMIN

SOC_G3

VLP ramps when VSYS input

power becomes sufficient high

I2C Register map is reset to

default settings

Main Battery becomes valid

USV or AC/DC Adapter Insertion

Table 6 : G3 State Transition

Event Trigger

Conditions (all

mandatory)

Next state

Note

Input power Source removal and

Main Battery Removal/Depletion

VSYS < VMIN

VBATBKUP>VMIN

DA6021 loses states, except

RTC powered registers

Restart with default values

except RTC powered registers

VSYS < VMIN

VBATBKUP<VMIN

DA6021 loses states, RTC

powered registers loses states

Re-start with default values

See event and conditions in Cold Boot Triggers

SOC_S4

DA6021 transitions to

SOC_S4 to start cold boot

sequence based on SOC

handshake

Table 7: SOC_G3 State Transition

VSYS

2.0V

2.375V

2.7V

3.0V

5.5V

POR_PMIC

5.6V

POR comparators

Programmable

Via OTP

VSYS Valid

Over Voltage

VSYS Under

Voltage

RESET

OTP/

EEPROM/

SOC_G3, SOC_S*

SOC_G3,

SOC_S*

SOC_G3

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