DA6021 datasheet(46/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

46 of 224

www.dialog-semiconductor.com

PWRSEQCFG

Address

0xDC

Page 0

Read

Reset Value

0x0E

MSB

LSB

R/W

Reserved

USBS

DPCFG

VCCA

PWROKCFG

SUSPWRD

NACKCFG

DTPWROK

Delay time for Core rails valid to VCCAPWROK and COREPWROK

assertion

1ms

10ms

100ms

120ms

SUSPWRDNACKCFG

When SLP_S4_B = 0, this bit decides if the power sequencer should go to

SOC_G3 state if the SUSPWRDNACK is asserted.

go to SOC G3 if SUSPWRDNACK = 1.

not go to SOC G3 regardless of SUSPWRDNACK status.

VCCAPWROKCFG

Option to de-assert VCCAPWROK when PMIC enters SOC S0IX state.

VCCAPWROK gets de-asserted (=0) when entering SOC S0IX.

VCCAPWROK remains asserted (=1) when entering SOC S0IX.

USBDPCFG

Option to set ILIM[1:0] for USB SDP current limit.

USB SDP, set ILIM[1:0] to 01 for 100mA current limit.

USB SDP, set ILIM[1:0] to 11 for 500mA current limit.

Warm Reset Sequence

10.3.2

During a warm reset the SoC will toggle the PLTRST_B pin for a certain amount of time. This sequence can only

happen while in SOC_S0 state. DA6021 captures this event in order to disable/idle the I2C interface and SVID

interface. All voltage rails remain in regulation, except VCC and VNN, as those will be re-programmed to VBOOT

voltage.

Enter SOC S0iX Mode

10.3.3

The S0iX state is entered when the SOC is in a shallow sleep state. This state is entered when the SOC asserts

the SLP_S0IX_B (LOW) pin to the PMIC. VDDQ_VTT and SX rails are turned off. The VCC rail is either turned

off by SVID commands (not by SLP_S0IX_B signal) or set to a voltage set in SVID address 0x39. The VNN rail

is set to a voltage set in SVID address 0x39.The rest of the VRs remain on but enters into power save mode.

VCCAPWROKCFG bit in register PWRSEQCFG provides the option to de-assert VCCAPWROK in S0IX state.

VCCAPWROKCFG =1, PMIC does not deassert VCCAPWROK when entering S0IX state,

VCCAPWROKCFG =0, PMIC deasserts VCCAPWROK after SLP_S0IX_B is asserted and before VRs start to

turn off when entering S0IX state.

The rail sequencing is shown in the figure below.

DA6021 Datasheet(PDF) 46 Page - Renesas Technology Corp

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