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DA6021 Datasheet(PDF) 75 Page - Renesas Technology Corp |
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DA6021 Datasheet(HTML) 75 Page - Renesas Technology Corp |
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75 / 225 page ![]() DA6021 HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR Company Confidential Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 75 of 224 www.dialog-semiconductor.com # Register Description Access Note supported” acknowledge. VR12 VID data format. Must be programmed by MASTER during boot up sequence if a value other than default is desired. Offset (33h) does not effect Vout_max. IE VID+offset can be > Vout_max. 0x31 VID setting Data register containing currently programmed VID voltage. VID data format. Default is 00h, zero volts out, VR off. Read/write 0x32 PWR state Register containing the current programmed power state. Default is 00h, normal power mode Read/write 0x33 Offset Sets offset in VID steps added to the VID setting for voltage margining. Bit 7 is sign bit, 0=positive margin, 1= negative margin. Remaining 7 BITS are _B VID steps for the margin 2s complement. 00h= no margin. 01h=+1 VID step, 02h=+2 VID steps FFh=- 1 VID step… Read/write 0x39 S0iX_SVID setting Data register containing the VID voltage that is used to DECAY to when the SLP_S0IX_B is asserted and PLTRST_B de-asserted; The voltage ramps back to 31h using fast ramp set in VSLEW(2Ah) at de-assertion of SLP_S0IX_B Read/write Table 35: SVID Supported Registers Register Name VENDOR_ID Address 0x00 Page 2/3 Read 0x00 MSB LSB R R R R R R R R VendorID[7:0] VendorID[7:0] 0x2B identifies Dialog Semiconductor Register Name PRODUCT_ID Address 0x01 Page 2/3 Read 0x00 MSB LSB R R R R R R R R ProductID[7:0] ProductID[7:0] 0 Identifies the product |
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