DA6021 datasheet(27/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

27 of 224

www.dialog-semiconductor.com

PLTRST_B

9.1.15

PLTRST_B is an active low dedicated input signal from the SOC that indicates the SOC already comes out of

reset upon de-assertion (PLTRST_B=1). Please note that PLTRST_B is not a power state indication signal while

SLP_S*_B (i.e. SLP_S0IX_B or SLP_S3_B or SLP_S4_B) signals are. PMIC ignores the PLTRST_B if it is in

one of the standby states.

SLP_S0iX_B

9.1.16

SLP_S0IX_B is an active low dedicated input signal from the SOC that indicates SX state entry upon assertion

(SLP_S0IX=LOW) and exit upon de-assertion (SLP_S0IX=HIGH). The assertion of the SLP_S0IX_B signal from

the SOC launches SOC_SX entry sequence. It is only considered if RSMRST_B=1.

SLP_S3_B

9.1.17

SLP_ S3_B is an active low dedicated input signal from the SOC that indicates S3 state entry upon assertion

(SLP_S3_B=LOW) and exit upon de-assertion (SLP_ S3_B=HIGH). The assertion/de-assertion of the

SLP_S3_B signal from the SOC launches SOC_S3 state entry/exit sequence. It is valid when RSMRST_B=1

(de-asserted).

SLP_S4_B

9.1.18

SLP_S4_B is an active low dedicated input signal from the SOC that indicates S4 state entry upon assertion

(SLP_S4_B=LOW) and exit upon de-assertion (SLP_S4_B=HIGH). The assertion/de-assertion of the SLP_S4_B

signal from the SOC launches SOC_S4 state entry/exit sequence. It is valid only when RSMRST_B=1.

RSMRST_B

9.1.19

RSMRST_B is an active low dedicated output signal. RSMRST_B asserts when voltage rail V3P3A is enabled.

RSMRST_B shall be actively driven to low in SOC G3 state when SUS rails are turned off. This is down via a

pull-down integrated resistor. The nominal voltage of RSMRST_B is 0V when asserted, 3.3V when de-asserted.

DRAMPWROK

9.1.20

DRAMPWROK is an active high dedicated output signal. DRAMPWROK asserts when voltage rail VDDQ is

enabled. The nominal voltage of DRAMPWROK is VDDQ when asserted, 0V when de-asserted.

VCCAPWROK

9.1.21

VCCAPWROK is an active high dedicated output signal. VCCAPWROK asserts when all voltage rails that are

supposed to be on in SOC_S0 and SOC_SX states are at nominal voltage. The nominal voltage of

VCCAPWROK is VDDQ when asserted, 0V when de-asserted. VCCAPWROK will de-assert only if both

PLTRST_B and SLP_S0IX_B are asserted (=0) during sleep state entry.

COREPWROK

9.1.22

COREPWROK is an active high dedicated output signal. COREPWROK asserts when all voltage rails that are

supposed to be on in SOC_S0 and SOC_SX states, are at nominal voltage. COREPOWROK shall be actively

driven to low in SOC G3 state when SUS rails (*_A rails) are turned off. The nominal voltage of COREPWROK is

3.3V when asserted, 0V when de-asserted. COREPWROK will de-assert only if both PLTRST_B and

SLP_S0IX_B are asserted (=0) during sleep state entry.

SUSPWRDNOK

9.1.23

SUSPWRDNACK is an active high dedicated input signal from the SOC that indicates the PMIC to turn off the

SUS rails (A) rails (V3P3A, V1P8A, V1P0A) in junction with assertion of SLP_S4_B. It is valid when

RSMRST_B=1 (de-asserted) and SLP=S4_B=0 (asserted).

BATLOW_B

9.1.24

BATLOW_B is an active low dedicated output signal to the SOC indicating that the battery voltage is not

sufficiently high to boot the SoC.

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