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DA6021 Datasheet(PDF) 44 Page - Renesas Technology Corp |
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DA6021 Datasheet(HTML) 44 Page - Renesas Technology Corp |
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44 / 225 page  DA6021 HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR Company Confidential Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 44 of 224 www.dialog-semiconductor.com Parameter Description Min [ms] Typ [ms] Max [ms] Measured [ms] T0 VUSBPHY Turn on Delay + Ramp-Up Time 0,08 2,00 T1 not measureable ---- T2_VUSBPHY Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,112 T2_V1P0A Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,357 T3_V1P0A- V1P8A Rail to Subsequent Rail Turn-On Delay 0,50 1,00 2,05 0,767 T2_V1P8A Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,672 T3_V1P8A- V1P2A Rail to Subsequent Rail Turn-On Delay 0,50 1,00 2,05 0,869 T2_V1P2A Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,051 T3_V1P2A- V3P3A Rail to Subsequent Rail Turn-On Delay 0,50 1,00 2,05 0,687 T2_V3P3A Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,295 T4 V3P3A valid to RSMRST_B deassertion 0,000 0,024 0,032 0,009 T5 RSMRST_B deassertion to SLP_S4_B deassertion 0,02 SOC related T6 SLP_S4_B deassertion to SUSPWRDNACK goes HIGH 0,00 SOC related T3_V3P3A- V1P8U Rail to Subsequent Rail Turn-On Delay 0,50 1,00 2,05 0,703 T7 SLP_S4_B deassertion to V1P8U turn-on delay 0,000 0,024 0,032 0,049 T2_V1P8U Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,102 T3_V1P8U-VDDQ Rail to Subsequent Rail Turn-On Delay 0,10 1,00 2,05 0,474 T2_VDDQ Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,473 T3_VDDQ- VREFDQ0 Rail to Subsequent Rail Turn-On Delay 0,50 1,00 2,05 0,707 T2_VREFDQ0 Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,014 T3_VREFDQ0- VREFDQ1 Rail to Subsequent Rail Turn-On Delay 0,00 0,013 T2_VREFDQ1 Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,015 T8 VREFDQ1 to DRAMPWROK assertion 0,000 0,024 0,032 0,018 T9 SLP_S4_B deassertion to SLP_S3_B deassertion 0,02 SOC related T3_VREFDQ1- V5P0S Rail to Subsequent Rail Turn-On Delay 0,50 1,00 2,05 0,566 T10 SLP_S3_B de-assertion to first S rail turn-on delay 0,000 3,000 6,166 0,015 T2_V5P0S Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,010 T3_V5P0S-VNN Rail to Subsequent Rail Turn-On Delay 0,20 1,00 2,05 0,259 T2_VNN Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,084 T3_VNN-VCC Rail to Subsequent Rail Turn-On Delay 0,20 1,00 2,05 0,257 T2_VCC Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,082 T3_VCC-V1P0S Rail to Subsequent Rail Turn-On Delay 0,20 1,00 2,05 0,238 T2_V1P0S Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,062 T3_V1P0S- V1P05S Rail to Subsequent Rail Turn-On Delay 0,10 1,00 2,05 0,109 |
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