DA6021 datasheet(38/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

38 of 224

www.dialog-semiconductor.com

10. Power Controller State Machine

Overview

10.1

The power controller state machine is the main state machine of DA6021. It is comprises a first phase related to

the power up sequence where all the condition for a safe boot are evaluated and the parameter are taken from

the OTP/EEPROM, and a second phase related to the SoC power sequence where all the power rails for the

SoC and platform are turned on according to certain sequencing rules.

The sequencer is very flexible in terms of components ordering and the intermediate delays between them.

Optionally the sequencer can wait for a certain condition, for example a breakpoint, an external programmed

trigger or waiting in a system power state like SOC_S4. In case of power-up direction, the components will be

enabled. In the power-down direction the components will be disabled.

The sequence configuration is stored in the OTP memory the contents of which are read out during the first

power up cycle. The sequencer also controls the clock request of different blocks. Refer to the Introduction

section on the power states for an overview on power up states and SoC sequencer states.

Power State Transitions

10.2

Figure 8: State Transitions

SOC_G3

(SPD)

SOC_S4

SOC_S3

SOC_S0

(Active)

SOC_SX

SYS_WAKEUP

UV_EVENT

VSYS_VALID

PH_EVENT

PH_EVENT |

D2G3 = 1

D2SX = 1

D2S3 = 1

D2S4 = 1

U2S3 = 1

U2SX = 1

U2S0 = 1

OTP

EEPROM

RESET

POR = 1

OTP_DONE = 1

EEPROM_DONE = 1

POR = 0 |

SOFT_RST = 1

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