DA6021 datasheet(45/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

45 of 224

www.dialog-semiconductor.com

T2_V1P05S

Ramp-Up time from 10% to 90% voltage

0,08

1,00

2,00

0,051

T3_V1P05S-

V1P8S

Rail to Subsequent Rail Turn-On Delay

0,10

1,00

2,05

0,237

T2_V1P8S

Ramp-Up time from 10% to 90% voltage

0,08

1,00

2,00

0,092

T3_V1P8S-

V1P2S

Rail to Subsequent Rail Turn-On Delay

0,10

1,00

2,05

0,155

T2_V1P2S

Ramp-Up time from 10% to 90% voltage

0,08

1,00

2,00

0,006

T3_V1P2S-

V3P3S

Rail to Subsequent Rail Turn-On Delay

0,10

1,00

2,05

0,173

T2_V3P3S

Ramp-Up time from 10% to 90% voltage

0,08

1,00

2,00

0,290

T3_V3P3S-

V2P285S

Rail to Subsequent Rail Turn-On Delay

0,10

1,00

2,05

0,108

T2_V2P85S

Ramp-Up time from 10% to 90% voltage

0,08

1,00

2,00

0,260

T11

SLP_S3_B deassertion to SLP_S0IX_B

deassertion

0,03

SOC

T3_V2P85S-

VDDQ_VTT

Rail to Subsequent Rail Turn-On Delay

0,10

1,00

2,05

0,260

T12

SLP_S0IX_B deassertion to first SX rail turn-on

delay

0,000

8,000

16,434

0,048

T2_VDDQ_VTT

Ramp-Up time from 10% to 90% voltage

0,08

1,00

2,00

0,006

T3_VDDQ_VTT-

V1P2SX

Rail to Subsequent Rail Turn-On Delay

0,50

1,00

2,05

0,053

T2_V1P2SX

Ramp-Up time from 10% to 90% voltage

0,08

1,00

2,00

0,0001

T3_V1P2SX-

V1P0SX

Rail to Subsequent Rail Turn-On Delay

0,10

1,00

2,05

0,017

T2_V1P0SX

Ramp-Up time from 10% to 90% voltage

0,08

1,00

2,00

0,061

T13

Core rails valid to VCCAPWEROK and

COREPWROK assertion

100

100,1

T14

COREPWROK assertion to PLTRST_B

deassertion

0,06

SOC

T15

MODEM_OFF_B deassertion Delay from

PLTRST_B deassertion

0,01

0,02

0,04

0,035

T16

SDWN_B deassertion Delay from PLTRST_B

deassertion

0,04

0,06

0,075

0,068

Table 18: Cold Boot Timings

As the regulators power-up times are load dependent, worst case times of 2ms are programmed. This will

guarantee that the rails have reached the target voltage. Optimization reducing the start-up time can be done

when power rail load conditions are clear or on the final product.

The delay time for “Core rails valid to VCCAPWEROK and COREPWROK assertion” is programmable by the

following register. The configuration bit for VCCAPWROK and SUSPWRDNOK are also included in the

PWRSEQCFG register (page 0), as defined below.

DA6021 Datasheet(PDF) 45 Page - Renesas Technology Corp

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