DA6021 datasheet(74/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

74 of 224

www.dialog-semiconductor.com

SVID Register Set

11.5.5

Description

Access

Note

0x00

Vendor ID

The vendor ID is defined by Intel . DA6021

returns the assigned vendor ID

Read only

0x01

Product ID

Identifies the DA6021 with its specific number

Read only

0x02

Product revision

This byte is slpit into the new release code

(NRC[3:0]) in the high nibble and the minor

revision code (MRC[3:0]) in the low nibble of

this byte.

Read only

0x06

Capability

current monitoring is supported

Read only

0x10

Status_1

Data register read after the alert_B signal is

asserted. Conveying the status of the VR.

Read only

0x14

VCC/VNN Output

Current, Imon (H)

Running 1 ms averaging (analog or digital),

approximately 1 ms register update. 10 bits

ADC, store MSB & 2

nd MSB of the ADC

output onto D[1..0] on this register

Read only

VCC in VCC

registers

VNN in VNN

registers

0x15

VCC/VNN Output

Current, Imon (L)

Running 1 ms averaging (analog or digital),

approximately 1 ms register update.

10 bits ADC, store the 1

st 8 LSB of the ADC

output onto this register.

Read only

VCC in VCC

registers

VNN in VNN

registers

0x1D

V1P0A/VDDQ

Output Current,

Imon (H)

Running 1 ms averaging (analog or digital),

approximately 1ms register update, 10 bits

ADC, store MSB & 2

nd MSB of the ADC

output onto D[1..0] on this register.

Read only

V1P0A in

VCC regs

VDDQ in

VNN regs

0x1E

V1P0A/VDDQ

Output Current,

Imon (L)

Running 1 ms averaging (analog or digital),

approximately 1ms register update, 10 bits

ADC, store the 1

st 8 LSB of the ADC output

onto this register.

Read only

V1P0A in

VCC regs

VDDQ in

VNN regs

0x1F

V1P05S Output

Current, Imon (H)

Running 1 ms averaging (analog or digital),

approximately 1ms register update, 10 bits

ADC, store MSB & 2

nd MSB of the ADC

output onto D[1..0] on this register.

Read only

V1P05S in

VCC regs

0x20

V1P05S Output

Current, Imon (L)

Running 1 ms averaging (analog or digital),

approximately 1ms register update, 10 bits

ADC, store the 1

st 8 LSB of the ADC output

onto this register.

Read only

V1P05S in

VCC regs

0x26

Vboot

Data register containing Vboot voltage. VR12

VID format, 0x97 = 1.0V

Read only

0x97 equals

to 1.0V

0x2A

Slew

Slew rate control register

0x2D

VCC/VNN Imon

accuracy

Data register containing the Imon error in

percentage. Binary Coded Decimal format in

%, IE 10% = 0x0A. This data is used with the

Imon register (0x14 & 0x15).

Read only

0x2E

V1P0A/VDDQ Imon

accuracy

Data register containing the Imon error in

percentage. Binary Coded Decimal format in

%, IE 10% = 0x0A. This data is used with the

Imon register (0x1D & 0x1E)

Read only

0x2F

V1P05S Imon

accuracy

Data register containing the Imon error in

percentage. Binary Coded Decimal format in

%, IE 10% = 0x0A. This data is used with the

Imon register (0x1F & 0x20)

Read only

0x30

Vout max

This register is programmable by the master

and sets the maximum VID the VR will

support. If a higher VID code is received, the

VR should respond with “Reject, not

Read/write

0xD3

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