DA6021 datasheet(70/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

70 of 224

www.dialog-semiconductor.com

NOTES:

1. V1P0S refers to instantaneous voltage at V1P0S_FB location.

2. Measured at 0.31 * V1P0S.

3. VIN between 0V and V1P0S.

4. CPAD includes die capacitance only. No package parasitic included.

Figure 23: Definition of VHYS

Symbol

Parameter

Min

Typ

Max

Units

Notes

Val

Vmax

VDS max open drain

buffer to accommodate

bus ringing

-1.00

3.30

SR Fall

Data/Alert

1.20

3.50

V/ns

Load:

Rpu=64.9

Ω

SR Rise

Data/Alert

1.20

3.50

V/ns

Load:

Rpu=64.9

Ω

Table 32: SVID buffer AC Electrical Parameters

Slew Rate (SR) is measured between 0.7*V1P0S and 0.3*V1P0S. SR is measured at the output of the buffer;

Rpu is connected to V1P0S as a load with no additional capacitance on the board. The slew rate is defined with

VR buffer capacitance only.

VCLK Timing Parameters

11.5.2

Symbol

Parameter

Min

Typ

Max

Units

Notes

Val

VCLK frequency

13.3

26.25

MHz

1,4

Thigh

VCLK high time

-10%

+10%

% of 0.5

Tperiod

2,4

Tlow

VCLK low time

-10%

+10%

% of 0.5

Tperiod

2,4

Trise

VCLK rise time @VR

Pad

0.25

3.0

Tfall

VCLK fall time @VR

Pad

0.25

3.0

Duty cycle

1,4

E,D

Table 33: VCLK AC Timing Parameters

NOTES:

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