DA6021 datasheet(9/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

9 of 224

www.dialog-semiconductor.com

Figure 57: I2C Fast Speed Read .............................................................................................................. 124

Figure 58: High Speed Write .................................................................................................................... 124

Figure 59: High Speed Read .................................................................................................................... 124

Figure 60: VBAT Input Detection .............................................................................................................. 126

Figure 61: Battery Single Wire Block Diagram for Analog sensing, Digital communication..................... 127

Figure 62: VSYS Valid Input Power Detection ......................................................................................... 129

Figure 63: USB Detection ......................................................................................................................... 129

Figure 64: DCIN Detection........................................................................................................................ 130

Figure 65: Valid Battery Thresholds ......................................................................................................... 131

Figure 66: SVTM Block Diagram .............................................................................................................. 158

Figure 67: BCU Warning Flag Generation................................................................................................ 161

Figure 68: VSYS Trip Points Flag Logic ................................................................................................... 164

Figure 69 : GPIO Block Diagram .............................................................................................................. 179

Figure 70: 1st Level Interrupts .................................................................................................................. 190

Figure 71 : Power/Utility Button Detection Logic ...................................................................................... 195

Figure 72: Power Button Boot Flow Diagram ........................................................................................... 196

Figure 73: Power Button Cold Off Flow Diagram ..................................................................................... 197

Figure 74: SVID Debug Port Bus Diagram ............................................................................................... 204

Figure 75: I2C Debug Port Bus Diagram .................................................................................................. 205

Figure 76: Package Outline Drawing and Dimensions ............................................................................. 220

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