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DA6021 Datasheet(PDF) 99 Page - Renesas Technology Corp

Part # DA6021
Description  HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR
PDF  225 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA6021 Datasheet(HTML) 99 Page - Renesas Technology Corp

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DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
99 of 224
www.dialog-semiconductor.com
S0ix State:
When the SoC enters the S0ix state, SLP_S0ix is held low. DA6021 turns the VDDQ buck regulator into low
power mode and disables all un-necessary blocks, reducing the power requirements. DA6021 exits this power
saving mode within 5µs after the SoC asserts the SLP_S0ix signal to high.
DA6021 is capable to support up to 200mA in this state.
S3 State:
In S3 state the average current of VDDQ is expected to be ~30mA which the regulator provides in power saving
mode.
11.6.6.2
Electrical Characteristics VDDQ
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Val
VDDQ_VIN
Input Voltage
2.7
4.5
V
-
Cin
at VDDQ_IN
2 x 4.7
µF
-
Cout
3 x 47 or 6 x 22
µF
-
ESR of output capacitor
6 @ 22/47µF
mΩ
-
ESL of output capacitor
1.6 @ 3MHz
nH
-
L_BUCK
inductor value
-20%
2 x 0.47
+20%
μH
-
L_DCR
inductor resistance
48
48
mΩ
-
V1P0A
Output Voltage
IOUT= Imax
1.24/1.35
2%
V
A
F_BUCK
Frequency of operation
3
MHz
A
Transient load profile
35-2085mA
200
ns
-
Transient droop
16
35-2085mA
50
mV
E
Transient overshoot
17
2085-35mA
50
mV
E
Ton
Turn on time
2
ms
E
Rpd
Discharge impedance
VDDQ .. 0V
20
Ω
A
IQ_ON
Quiescent Current in On
Mode
100
50
µA
E
Normal Mode
– Synchronous rectification (PWM)
Maximum Output Current (Imax)
2800
mA
D
ILIMIT
Current limitation
Cycle by cycle
1.3*Imax
mA
A*
Efficiency at VSYS = 3.7V & Tamb=60°C with
proposed external components and PCB
layout
See Figure 39
D,E
,A*
18
Sleep Mode
– Pulse skipping (PSK)
Efficiency at VSYS = 3.7V & Tamb=60°C with
proposed external components and PCB
layout
See Figure 39
D,E
,A*
Table 56: Electrical Parameter for BUCK_VDDQ
16 Including DC accuracy, ripple and load regulation
17 Including DC accuracy, ripple and load regulation
18 RDSON measurement on ATE



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