DA6021 datasheet(35/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

35 of 224

www.dialog-semiconductor.com

SOC S4 State

9.3.4

The entering and exiting of each the SOC S4 state is controlled by a signal which is delivered to the PMIC by the

SOC via a dedicated physical pin SLP_S4_B. The exiting of SLP_S4_B is also gated by BATLOW_B.



Rails that are on:

They are shown in the power sequencing diagrams

VRs shall be placed in PFM/power save mode

Internal PMIC rails



Interfaces available:

SVID is OFF in S4

I2C is OFF in S4



Input source comparators and interrupts active.



All registers powered, with states retained.



Thermal monitoring and VR current measurements are disabled by default. If enabled, the measurements

are taken at standby frequency.

The events causing a transition out of the ‘SOC S4’ state are shown in the table below.

Event Trigger

Conditions (all

mandatory)

Next state

Note

Input power Source removal and

Main Battery Removal/Depletion

VSYS < VMIN

VBATBKUP>VMIN

DA6021 loses states, except

RTC powered registers

Restart with default values

except RTC powered registers

VSYS < VMIN

VBATBKUP<VMIN

DA6021 loses states, RTC

powered registers loses states

Re-start with default values

See event and conditions in Cold off Triggers

SOC_G3

See “Cold Off Triggers”

Power Button Held

Power Button held time

< PBCONFIG

.FCOT[3:0]

If exit S4 to SOC_S3,

BATLOW_B=1

SOC_S3

DA6021 passes PWRBTN_B

information to SoC. SoC

toggles first SLP_S4_B=1 to

exit S4 state, then

SLP_S3_B=1 to exit S3 state

followed by SLP_S0iX_B = 1

to exit S0iX

SLP_S3_B

SLP_S4_B =1

BATLOW_B=1

SOC_S3

Exit S4 state

SLP_S4_B

SLP_S4_B=0

SUSPWRDNACK=1

SUSPWRDNACKCFG=1

SOC_G3

SOC can toggle

SUSPWRDNACK to 1 when

SLP_S4_B=0 to enter

SOC_G3 state

Table 11: SOC S4 State Transition

Truth Table of Sleep Signals and DA6021 Final Power States

9.3.5

SUSPWDNA

SUSPWRDN

ACKCFG

SLP_S4_B

SLP_S3_B

SLP_S0iX_B

Final Power

State

Comment

SOC_G3

Note 5

SOC_S4

Note 5

SOC_S4

Note 5

SOC_S3

Note 6

SOC_S0iX

Note 7

SOC_S0

Note 7

Table 12: Truth Table of Sleep Signals and DA6021 Final Power States

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