DA6021 datasheet(52/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

52 of 224

www.dialog-semiconductor.com

Parameter

Description

Min

[ms]

Typ

[ms]

Max

[ms]

Measured

[ms]

SLP_S0IX_B deassertion to first SX rail turn-on

delay

0,000

0,008

0,016

0,006

T1_V1P05S

Ramp-Up time from 10% to 90%

0,04

0,08

0,16

0,033

T2_V1P05S-

VDDQ_VTT

Rail to Subsequent Rail Turn-On Delay

0,00

0,05

0,10

0,028

T1_VDDQ_VTT

Ramp-Up time from 10% to 90%

0,04

0,08

0,16

0,007

T2_VDDQ_VTT-

V1P2SX

Rail to Subsequent Rail Turn-On Delay

0,00

0,05

0,10

0,053

T1_V1P2SX

Ramp-Up time from 10% to 90%

0,04

0,08

0,16

0,0001

T2_V1P2SX-

V1P0SX

Rail to Subsequent Rail Turn-On Delay

0,00

0,05

0,10

0,017

T1_V1P0SX

Ramp-Up time from 10% to 90%

0,04

0,08

0,16

0,062

Total S0IX exit latency: from SLP_S0IX_B de-

assertion to all VRs up

0,200

0,169

Time from All VRs are valid to VCCAPWEROK

assertion

0,000

0,008

0,016

0,013

Table 20: Exit S0iX timing

Enter SOC S3 Mode

10.3.5

The S3 state is entered when the SOC asserts the SLP_S3_B pin (LOW). VRs that remain on enter into power

saving mode.

The rail sequencing is shown in the figure below.

DA6021 Datasheet(PDF) 52 Page - Renesas Technology Corp

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