PM7375-SC datasheet(116/430 Pages) PMC

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PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

100

10.1

Selectable Master Registers

Selectable Master registers can be accessed by either the PCI Host or the

microprocessor as configured by input, MPENB. It is expected that the master is

selected when the device is powered up. For each register description below, the

hexadecimal register number indicates the address of the register when accesses

are made using the microprocessor port. The hexadecimal number in brackets

indicates the PCI offset from the base address in the LASAR-155 Memory Base

Address Register when accesses are made using the PCI Host Port.

10.1.1

Bit

Type

Function

Default

Bit 15

R/W

RESET

Bit 14

Unused

Bit 13

Unused

Bit 12

Unused

Bit 11

Unused

Bit 10

Unused

Bit 9

Unused

Bit 8

Unused

Bit 7

Unused

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

Writing to this register simultaneously loads all the performance meter registers in

the RSOP, RLOP, RPOP, RACP, TACP, SAR PMON blocks. A maximum of 7 µs are

required to load all registers after a write.

PM7375-SC Datasheet(PDF) 116 Page - PMC-Sierra, Inc

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