Electronic Components Datasheet Search
  English  ▼

X  

PM7375-SC Datasheet(PDF) 160 Page - PMC-Sierra, Inc

Part # PM7375-SC
Description  LOCAL ATM SAR & PHYSICAL LAYER
PDF  430 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7375-SC Datasheet(HTML) 160 Page - PMC-Sierra, Inc

Back Button PM7375-SC Datasheet HTML 156Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 157Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 158Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 159Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 160Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 161Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 162Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 163Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 164Page - PMC-Sierra, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 160 / 430 page
background image
PM7375 LASAR-155
DATA SHEET
PMC-931127
ISSUE 6
LOCAL ATM SAR & PHYSICAL LAYER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
144
10.1.38
Register 0x41 (0x104): TPOP Pointer Control
Bit
Type
Function
Default
Bit 15
Unused
X
Bit 14
Unused
X
Bit 13
Unused
X
Bit 12
Unused
X
Bit 11
Unused
X
Bit 10
Unused
X
Bit 9
Unused
X
Bit 8
Unused
X
Bit 7
Unused
X
Bit 6
R/W
FTPTR
0
Bit 5
R/W
SOS
0
Bit 4
R/W
PLD
0
Bit 3
R/W
NDF
0
Bit 2
R/W
NSE
0
Bit 1
R/W
PSE
0
Bit 0
R/W
Reserved
0
This register allows control over the transmitted payload pointer for diagnostic
purposes.
PSE:
The PSE bit controls the insertion of positive pointer movements. A zero to one
transition on this bit enables the insertion of a single positive pointer justification
in the outgoing stream. This register bit is automatically cleared when the pointer
movement is inserted. This bit has no effect if the FIXPTR bit of the Master
Control register is a logic 1.
NSE:
The NSE bit controls the insertion of negative pointer movements. A zero to one
transition on this bit enables the insertion of a single negative pointer justification
in the outgoing stream. This register bit is automatically cleared when the pointer
movement is inserted. This bit has no effect if the FIXPTR bit of the Master
Control register is a logic 1.
NDF:
The NDF bit controls the insertion of new data flags in the inserted payload
pointer. When a logic one is written to this bit position, the pattern contained in
the NDF[3:0] bit positions in the TPOP Arbitrary Pointer MSB Register is inserted



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com