| Electronic Components Datasheet Search |
|
PM7375-SC Datasheet(PDF) 161 Page - PMC-Sierra, Inc |
|
|
|||||||||||||||||||||||||||||
PM7375-SC Datasheet(HTML) 161 Page - PMC-Sierra, Inc |
|
161 / 430 page ![]() PM7375 LASAR-155 DATA SHEET PMC-931127 ISSUE 6 LOCAL ATM SAR & PHYSICAL LAYER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 145 continuously in the payload pointer. When a logic zero is written to this bit position, the normal pattern (0110B) is inserted in the payload pointer. PLD: The PLD bit controls the loading of the pointer value contained in the TPOP Arbitrary Pointer Registers. Normally, the TPOP Arbitrary Pointer Registers are written to set up the arbitrary new pointer value and a logic one is then written to this bit position to load the new pointer value. If a legal value (i.e. 0 • pointer value • 782) is transferred from the TPOP Arbitrary Pointer Registers, the transmit payload pointer will immediately change to the corresponding byte position. If a value greater than 782 is transferred, the payload pointer remains unchanged. This bit is automatically cleared after the new payload pointer has been loaded. This bit has no effect if the FIXPTR bit of the Master Control register is a logic 1. SOS: The SOS bit controls the stuff opportunity spacing between consecutive SPE positive or negative stuff events. When SOS is a logic zero, stuff events may be generated every frame as controlled by the PSE and NSE register bits described above. When SOS is a logic one, stuff events may be generated at a maximum rate of once every four frames. FTPTR: The force transmit pointer bit (FTPTR) enables the insertion of the pointer value contained in the TPOP Arbitrary Pointer Registers into the transmit stream for diagnostic purposes. This allows upstream payload mapping circuitry to continue functioning normally and a valid SPE to continue to be generated, although it is unlikely to be extracted by far end circuitry which should be in a loss of pointer state. If FTPTR is set to logic 1, the APTR[9:0] bits of the TPOP Arbitrary Pointer Registers are inserted into the H1 and H2 bytes of the transmit stream. At least one corrupted pointer is guaranteed to be sent. If FTPTR is a logic 0, a valid pointer is inserted. Reserved: The reserved bit must be programmed to logic zero for proper operation. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |