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PM7375-SC Datasheet(PDF) 178 Page - PMC-Sierra, Inc |
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PM7375-SC Datasheet(HTML) 178 Page - PMC-Sierra, Inc |
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178 / 430 page ![]() PM7375 LASAR-155 DATA SHEET PMC-931127 ISSUE 6 LOCAL ATM SAR & PHYSICAL LAYER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 162 10.1.62 Register 0x60 (0x180): TACP Control/Status Bit Type Function Default Bit 15 Unused X Bit 14 Unused X Bit 13 Unused X Bit 12 Unused X Bit 11 Unused X Bit 10 Unused X Bit 9 Unused X Bit 8 Unused X Bit 7 R/W Reserved 0 Bit 6 R Reserved X Bit 5 R Reserved X Bit 4 R/W DHEC 0 Bit 3 R/W Reserved 0 Bit 2 R/W HECADD 1 Bit 1 R/W DSCR 0 Bit 0 R/W FIFORST 0 FIFORST: The FIFORST bit is used to reset the internal four cell transmit FIFO. When FIFORST is set to logic zero, the FIFO operates normally. When FIFORST is set to logic one, the FIFO is immediately emptied and ignores writes. The FIFO remains empty and continues to ignore writes until a logic zero is written to FIFORST. DSCR: The DSCR bit controls the scrambling of the cell payload. When DSCR is a logic one, cell payload scrambling is disabled. When DSCR is a logic zero, payload scrambling is enabled. HECADD: The HECADD bit controls the addition of the coset polynomial, x6+x4+x2+1, to the HEC octet prior to insertion in the synchronous payload envelope. When HECADD is a logic one, the polynomial is added, and the resulting HEC is inserted. When HECADD is a logic zero, the polynomial is not added, and the unmodified HEC is inserted. |
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