ADXL366 datasheet(49/71 Pages) AD

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Data Sheet

ADXL366

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Rev. 0 | 49 of 71

Table 54. Bit Descriptions for TAP_LATENT (Continued)

Bits

Bit Name

Settings

Description

Reset

Access

during which a possible second tap event can be detected. The scale factor is 1.25ms/LSB. A value of

0 disables the double tap function.

TAP WINDOW REGISTER

Address: 0x32, Reset: 0x00, Name: TAP_WINDOW

Table 55. Bit Descriptions for TAP_WINDOW

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

TAP_WINDOW

The TAP_WINDOW register is 8 bits and contains an unsigned time value representing the amount

of time after the expiration of the latency time (determined by the latent register) during which a

second valid second tap (double tap) must occur to be considered a valid double tap. The scale

factor is 1.25ms/LSB.

0x0

R/W

X-AXIS USER OFFSET REGISTER

Address: 0x33, Reset: 0x00, Name: X_OFFSET

Table 56. Bit Descriptions for X_OFFSET

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

RESERVED

Reserved.

0x0

[4:0]

X_USER_OFFSET

User X-Axis Offset Calibration That Uses a 15mg/LSB Scale Factor. This calibration is in a twos

complement format where Bit 4 is the sign bit. These bits can be used to shift the offset of the

device. Note that this trim setting shares the same headroom as the factory trim setting. In other

words, a device with a high offset may have less room available for the user to trim.

0x0

R/W

Y-AXIS USER OFFSET REGISTER

Address: 0x34, Reset: 0x00, Name: Y_OFFSET

Table 57. Bit Descriptions for Y_OFFSET

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

RESERVED

Reserved.

0x0

[4:0]

Y_USER_OFFSET

User Y-Axis Offset Calibration that Uses a 15mg/LSB Scale Factor. This calibration is in a twos

complement format where Bit 4 is the sign bit. These bits can be used to shift the offset of the

device. Note that this trim setting shares the same headroom as the factory trim setting. In other

words, a device with a high offset may have less room available for the user to trim.

0x0

R/W

Z-AXIS USER OFFSET REGISTER

Address: 0x35, Reset: 0x00, Name: Z_OFFSET

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