ADXL366 datasheet(67/71 Pages) AD

67 / 71 page

Data Sheet

ADXL366

APPLICATIONS INFORMATION

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Rev. 0 | 67 of 71

Alternate Functions of Interrupt Pins

The INT1 pin and INT2 pin can be configured for use as input

pins instead of for signaling interrupts. INT1 is used as an external

clock input when the EXT_CLK bit (Bit 6) in the POWER_CTL

for synchronized sampling when the EXT_SAMPLE bit (Bit 3) in

the FILTER_CTL register (Address 0x2C) is set. One or both of

these alternate functions can be used concurrently. However, if an

alternate function of an interrupt pin is used, the interrupt pin cannot

simultaneously be used for its primary function, to signal interrupts.

External clocking and data synchronization are described in the

Applications Information section.

Activity and Inactivity Interrupts

The ACT bit (Bit 4) and INACT bit (Bit 5) in the STATUS register are

set when activity and inactivity are detected, respectively. Detection

procedures and criteria are described in the Motion Detection

section.

External ADC Interrupt

The ADXL366 incorporates a 14-bit ADC for digitization of an

external analog input. An interrupt can be generated based on the

user set threshold of the external ADC. For the battery powered de-

vice, the external ADC can be used to monitor the supply voltage.

After the supply voltage is lower than the specified threshold, an

interrupt can be generated to alert the end user to charge/change

the battery. By using this function, the host processor does not have

to use one more ADC to check the power supply periodically.

Data Ready Interrupt

The DATA_READY bit (Register 0x0B, Bit 0) is set when new valid

data is available, and it is cleared when no new data is available.

The DATA_READY bit is not set while any of the data registers,

Address 0x08 to Address 0x0A and Address 0x0E to Address 0x15,

are being read. If DATA_READY = 0 prior to a register read

and new data becomes available during the register read, DA-

TA_READY remains at 0 until the read is complete and, only then,

is set to 1.

If DATA_READY = 1 prior to a register read, it is cleared at the start

of the register read.

If DATA_READY = 1 prior to a register read and new data becomes

available during the register read, DATA_READY is cleared to 0 at

the start of the register read and remains at 0 throughout the read.

When the read is complete, DATA_READY is set to 1.

Using FIFO Interrupts

FIFO Watermark

The FIFO_WATERMARK bit (Register 0x0B, Bit 2) is set when

the number of samples stored in the FIFO is equal to or ex-

ceeds the number of samples specified in the FIFO_SAMPLES

the FIFO_CONTROL register (Bit 2, Address 0x28). The FIFO_WA-

TERMARK bit is cleared automatically when enough samples are

read from the FIFO so that the number of samples remaining is

lower than the value set by the user in the FIFO_SAMPLES bit

field.

If the number of FIFO samples is set to 0, the FIFO watermark

interrupt is set. To avoid unexpectedly triggering this interrupt, the

default value of the FIFO_SAMPLES register is 0x80.

FIFO Ready

The FIFO_READY bit (Register 0x44, Bit 1) is set when there is at

least one valid sample available in the FIFO output buffer. This bit is

cleared when no valid data is available in the FIFO.

Overrun

The FIFO_OVERRUN bit (Register 0x44, Bit 3) is set when the

FIFO has overrun or overflowed, indicating that new data has

replaced unread data. This may indicate a full FIFO that has not yet

been emptied or a clocking error caused by a slow SPI transaction.

If the FIFO is configured to oldest saved mode, an overrun event

indicates that there is insufficient space available for a new sample.

The FIFO_OVERRUN bit is cleared automatically when the con-

tents of the FIFO are read. Likewise, when the FIFO is disabled, the

FIFO_OVERRUN bit is cleared.

USING EXTERNAL TRIGGER

For applications that require a precisely timed acceleration meas-

urement, the ADXL366 features an option to synchronize accelera-

tion sampling to an external trigger. The EXT_SAMPLE bit (Bit 3)

in the FILTER_CTL register (Address 0x2C) enables this feature.

When the EXT_SAMPLE bit is set to 1, the INT2 pin is automatical-

ly reconfigured for use as the synchronization trigger input. Note

that the external trigger only works in measurement mode.

When external triggering is enabled, it is up to the system designer

to ensure that the sampling frequency meets system requirements.

Sampling too infrequently causes aliasing. Noise can be lowered

by oversampling. However, sampling at too high frequency may not

allow enough time for the accelerometer to process the acceleration

data and convert it to valid digital output.

When Nyquist criteria are met, signal integrity is maintained. An

internal anti-aliasing filter is available in the ADXL366 and can

assist the system designer in maintaining signal integrity. To prevent

aliasing, set the filter bandwidth to a frequency no greater than ½

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