ADXL366 datasheet(29/71 Pages) AD

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Data Sheet

ADXL366

SERIAL COMMUNICATIONS

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The ADXL366 communicates via a 4-wire SPI or I2C interface and

operates as a subordinate. Ignore data that is transmitted from the

ADXL366 to the main device during writes to the ADXL366.

As shown in Figure 2 to Figure 7, the MISO pin is in a high

impedance state (held by a bus keeper) except when the ADXL366

is sending read data, which is done to conserve bus power.

Wire the ADXL366 for SPI communication, as shown in the connec-

tion diagram in Figure 55. The recommended SPI clock speeds are

1MHz to 8MHz, with a 12pF maximum loading.

The ADXL366 uses an SPI mode with a clock polarity (CPOL) of

zero and a clock phase (CPHA) of zero.

For correct operation of the device, the logic thresholds and timing

parameters in Table 2 and Table 3 must be met at all times.

Refer to Figure 10 and Figure 11 for visual diagrams of the timing

parameters.

Figure 55. 4-Wire SPI Connection Diagram

SPI COMMANDS

The SPI port uses a multibyte structure where the first byte is a

command. The ADXL366 command set is as follows:

►

0x0A: write register

►

0x0B: read register

►

0x0D: read FIFO

Read and Write Register Commands

The command structure for the read register and write register

commands is </CS down> <command byte (0x0A or 0x0B)> <ad-

dress byte> <data byte> <additional data bytes for multi-byte>

… </CS up>.

The read and write register commands support multibyte (burst)

read/write access. The waveform diagrams for multibyte read and

write commands are shown in Figure 2 and Figure 3.

Read FIFO Command

Reading from the FIFO buffer is a command structure that does not

have an address, </CS down> <command byte (0x0D)> <data

byte> <data byte> … </CS up>.

It is recommended that a full sample set be read (using a multibyte

transaction). If a full sample set is not read using a multibyte

transaction, FIFO can get discarded and the channel ID can slip

out of synchronization. Data is presented most significant byte first,

followed by the least significant byte.

MULTIBYTE TRANSFERS

Multibyte transfers, also known as burst transfers, are supported

for all SPI commands (register read, register write, and FIFO read

commands). It is recommended that data be read using multibyte

transfers to ensure that a concurrent and complete set of x-axis,

y-axis, and z-axis acceleration (and temperature, where applicable)

data is read.

The FIFO runs on the serial port clock during FIFO reads and can

sustain bursting at the SPI clock rate as long as the SPI clock is

fast enough to pop data faster than it is being written to the FIFO

(depends on ODR).

A register read or write command begins with the address specified

in the command and auto-increments for each additional byte in

the transfer. Register 0x00 to Register 0x45 are user accessible. A

multibyte register read that extends past Register 0x45 gives valid

data only up to Register 0x45. Any attempt to read a higher register

may result in invalid data.

INVALID ADDRESSES AND ADDRESS

ALIASING

The ADXL366 has a 7-bit address bus, mapping only 128 regis-

ters in the possible 256 register address space. Register 0x00 to

attempt to read beyond Register 0x7F results in invalid data.

LATENCY RESTRICTIONS

Reading any of the data registers (Register 0x08 to Register 0x0A

or Register 0x0E to Register 0x17) clears the data ready interrupt.

There can be as much as a 120µs delay from reading a register

to the clearing of the data ready interrupt. This delay can increase

to 420μs in wake-up mode. Same delay applies to clear any other

interrupt on STATUS, STATUS_COPY, and STATUS_2 registers.

Other register reads, register writes, and FIFO reads have no

latency restrictions.

INVALID COMMANDS

There are only three valid SPI commands for the ADXL366, 0x0A,

0x0B, and 0x0D. All other commands are invalid and must be

avoided. When not receiving a valid command, the MISO output

remains in a high impedance state, and the bus keeper holds the

MISO line at its last value.

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