HD64F36049 datasheet(382/562 Pages) RENESAS

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Section 18 I

2C Bus Interface 2 (IIC2)

Rev. 3.00 Mar. 15, 2006 Page 350 of 526

REJ09B0060-0300

18.3.4

2C Bus Interrupt Enable Register (ICIER)

ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be

transferred, and confirms acknowledge bits to be received.

Bit

Bit Name

Initial

Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When the TDRE bit in ICSR is set to 1, this bit enables

or disables the transmit data empty interrupt (TXI).

0: Transmit data empty interrupt request (TXI) is

disabled.

1: Transmit data empty interrupt request (TXI) is

enabled.

TEIE

R/W

Transmit End Interrupt Enable

This bit enables or disables the transmit end interrupt

(TEI) at the rising of the ninth clock while the TDRE bit

in ICSR is 1. TEI can be canceled by clearing the TEND

bit or the TEIE bit to 0.

0: Transmit end interrupt request (TEI) is disabled.

1: Transmit end interrupt request (TEI) is enabled.

RIE

R/W

Receive Interrupt Enable

This bit enables or disables the receive data full

interrupt request (RXI) and the overrun error interrupt

request (ERI) with the clocked synchronous format,

when a receive data is transferred from ICDRS to

ICDRR and the RDRF bit in ICSR is set to 1. RXI can

be canceled by clearing the RDRF or RIE bit to 0.

0: Receive data full interrupt request (RXI) and overrun

error interrupt request (ERI) with the clocked

synchronous format are disabled.

1: Receive data full interrupt request (RXI) and overrun

error interrupt request (ERI) with the clocked

synchronous format are enabled.

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