HD64F36049 datasheet(405/562 Pages) RENESAS

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Section 18 I

2C Bus Interface 2 (IIC2)

Rev. 3.00 Mar. 15, 2006 Page 373 of 526

REJ09B0060-0300

18.5

Interrupts

There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,

NACK receive, STOP recognition, and arbitration lost/overrun error. Table 18.3 shows the

contents of each interrupt request.

Table 18.3

Interrupt Requests

Interrupt Request

Abbreviation

Interrupt Condition

2C Mode

Clocked

Synchronous

Mode

Transmit Data Empty

TXI

(TDRE=1) • (TIE=1)

Transmit End

TEI

(TEND=1) • (TEIE=1)

Receive Data Full

RXI

(RDRF=1) • (RIE=1)

STOP Recognition

STPI

(STOP=1) • (STIE=1)

NACK Receive

Arbitration

Lost/Overrun Error

NAKI

{(NACKF=1)+(AL=1)} •

(NAKIE=1)

When interrupt conditions described in table 18.3 are 1 and the I bit in CCR is 0, the CPU

executes an interrupt exception processing. Interrupt sources should be cleared in the exception

processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to

ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the

same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive

data of one byte may be transmitted.

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