HD64F36049 datasheet(407/562 Pages) RENESAS

407 / 562 page

Section 18 I

2C Bus Interface 2 (IIC2)

Rev. 3.00 Mar. 15, 2006 Page 375 of 526

REJ09B0060-0300

18.7

Usage Notes

18.7.1

Issue (Retransmission) of Start/Stop Conditions

In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing

under the following condition 1 or 2, such conditions may not be output successfully. To avoid

this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check

the SCLO bit in the I

2C control register 2 (IICR2) to confirm the fall of the ninth clock.

1. When the rising of SCL falls behind the time specified in section 18.6, Bit Synchronous

Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)

2. When the bit synchronous circuit is activated by extending the low period of eighth and ninth

clocks, that is driven by the slave device

18.7.2

WAIT Setting in I

2C Bus Mode Register (ICMR)

If the WAIT bit is set to 1, and the SCL signal is driven low for two or more transfer clocks by the

slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. To

avoid this, set the WAIT bit in ICMR to 0.

HD64F36049 Datasheet(PDF) 407 Page - Renesas Technology Corp