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HD64F36049 Datasheet(PDF) 406 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 406 Page - Renesas Technology Corp |
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406 / 562 page ![]() Section 18 I 2C Bus Interface 2 (IIC2) Rev. 3.00 Mar. 15, 2006 Page 374 of 526 REJ09B0060-0300 18.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull- up resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 18.21 shows the timing of the bit synchronous circuit and table 18.4 shows the time when SCL output changes from low to Hi-Z then SCL is monitored. SCL V IH SCL monitor timing reference clock Internal SCL Figure 18.21 Timing of Bit Synchronous Circuit Table 18.4 Time for Monitoring SCL CKS3 CKS2 Time for Monitoring SCL 0 7.5 tcyc 0 1 19.5 tcyc 0 17.5 tcyc 1 1 41.5 tcyc |
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