HD64F36049 datasheet(126/562 Pages) RENESAS

126 / 562 page

Section 7 ROM

Rev. 3.00 Mar. 15, 2006 Page 94 of 526

REJ09B0060-0300

7.2.4

Flash Memory Power Control Register (FLPWCR)

FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI

switches to subactive mode. There are two modes: mode in which operation of the power supply

circuit of flash memory is partly halted in power-down mode and flash memory can be read, and

mode in which even if a transition is made to subactive mode, operation of the power supply

circuit of flash memory is retained and flash memory can be read.

Bit

Bit Name

Initial

Value

R/W

Description

PDWND

R/W

Power-Down Disable

When this bit is 0 and a transition is made to subactive

mode, the flash memory enters the power-down mode.

When this bit is 1, the flash memory remains in the

normal mode even after a transition is made to

subactive mode.

6 to 0

—

All 0

—

Reserved

These bits are always read as 0.

7.2.5

Flash Memory Enable Register (FENR)

Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,

FLMCR1, FLMCR2, EBR1, and FLPWCR.

Bit

Bit Name

Initial

Value

R/W

Description

FLSHE

R/W

Flash Memory Control Register Enable

Flash memory control registers can be accessed when

this bit is set to 1. Flash memory control registers

cannot be accessed when this bit is set to 0.

—

R/W

Reserved

This bit can be read from or written to, but should not be

set to 1.

5 to 0

—

All 0

—

Reserved

These bits are always read as 0.

HD64F36049 Datasheet(PDF) 126 Page - Renesas Technology Corp

HD64F36049 Datasheet(HTML) 126 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL