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HD64F36049 Datasheet(PDF) 272 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 272 Page - Renesas Technology Corp |
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272 / 562 page ![]() Section 14 Timer Z Rev. 3.00 Mar. 15, 2006 Page 240 of 526 REJ09B0060-0300 B. External clock operation An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TCR, and a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the rising edge, falling edge, or both edges can be selected. The pulse width of the external clock needs two or more system clocks. Note that an external clock does not operate correctly with the lower pulse width. Figure 14.11 illustrates the detection timing of the rising and falling edges. TCNT External clock input pin TCNT input N-1 N N+1 φ Figure 14.11 Count Timing at External Clock Operation (Both Edges Detected) |
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