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HD64F36049 Datasheet(PDF) 321 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 321 Page - Renesas Technology Corp |
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321 / 562 page ![]() Section 15 Watchdog Timer Rev. 3.00 Mar. 15, 2006 Page 289 of 526 REJ09B0060-0300 Section 15 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 15.1. φ Internal reset signal PSS TCWD TMWD TCSRWD [Legend] TCSRWD: TCWD: PSS: TMWD: Timer control/status register WD Timer counter WD Prescaler S Timer mode register WD Internal oscillator CLK Figure 15.1 Block Diagram of Watchdog Timer 15.1 Features • Selectable from nine counter input clocks. Eight clock sources ( φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, and φ/8192) or the internal oscillator can be selected as the timer-counter clock. When the internal oscillator is selected, it can operate as the watchdog timer in any operating mode. • Reset signal generated on counter overflow An overflow period of 1 to 256 times the selected clock can be set. |
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