HD64F36024 datasheet(56/384 Pages) RENESAS

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Section 2 CPU

Rev. 4.00 Sep. 23, 2005 Page 30 of 354

REJ09B0025-0400

2.5

Addressing Modes and Effective Address Calculation

The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the

generated 24-bit address, so the effective address is 16 bits.

2.5.1

Addressing Modes

The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses

a subset of these addressing modes. Addressing modes that can be used differ depending on the

instruction. For details, refer to Appendix A.4, Combinations of Instructions and Addressing

Modes.

Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer

instructions can use all addressing modes except program-counter relative and memory indirect.

Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode

to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or

immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.10

Addressing Modes

No.

Addressing Mode

Symbol

@ERn

@(d:16,ERn)/@(d:24,ERn)

@ERn+

@–ERn

Absolute address

@aa:8/@aa:16/@aa:24

Immediate

#xx:8/#xx:16/#xx:32

Program-counter relative

@(d:8,PC)/@(d:16,PC)

Memory indirect

@@aa:8

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