HD64F36024 datasheet(71/384 Pages) RENESAS

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Section 3 Exception Handling

Rev. 4.00 Sep. 23, 2005 Page 45 of 354

REJ09B0025-0400

Section 3 Exception Handling

Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.

• Reset

A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared

by the

RES pin. The chip is also reset when the watchdog timer overflows, and exception handling

starts. Exception handling is the same as exception handling by the

RES pin.

• Trap Instruction

Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction

generates a vector address corresponding to a vector number from 0 to 3, as specified in the

instruction code. Exception handling can be executed at all times in the program execution state.

• Interrupts

External interrupts other than NMI and internal interrupts other than address break are masked by

the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the

current instruction or exception handling ends, if an interrupt request has been issued.

3.1

Exception Sources and Vector Address

Table 3.1 shows the vector addresses and priority of each exception handling. When more than

one interrupt is requested, handling is performed from the interrupt with the highest priority.

Table 3.1

Exception Sources and Vector Address

Relative Module

Exception Sources

Vector Number Vector Address

Priority

RES pin

Watchdog timer

Reset

H'0000 to H'0001

High



Reserved for system use

1 to 6

H'0002 to H'000D

External interrupt

NMI

H'000E to H'000F

CPU

Trap instruction (#0)

H'0010 to H'0011

(#1)

H'0012 to H'0013

(#2)

H'0014 to H'0015

(#3)

H'0016 to H'0017

Address break

Break conditions satisfied

H'0018 to H'0019

Low

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