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HD64F36024 Datasheet(PDF) 100 Page - Renesas Technology Corp |
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HD64F36024 Datasheet(HTML) 100 Page - Renesas Technology Corp |
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100 / 384 page ![]() Section 6 Power-Down Modes Rev. 4.00 Sep. 23, 2005 Page 74 of 354 REJ09B0025-0400 Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling DTON SSBY SMSEL Transition Mode after SLEEP Instruction Execution Transition Mode due to Interrupt 0 0 0 Sleep mode Active mode 0 1 Subsleep mode Active mode 1 X Standby mode Active mode 1 X 0* Active mode (direct transition) — Legend: X: Don’t care. * When a state transition is performed while SMSEL is 1, timer V, SCI3, SCI3_2, SCI3_3 (only for the H8/36024) and the A/D converter are reset, and all registers are set to their initial values. To use these functions after entering active mode, reset the registers. Table 6.3 Internal State in Each Operating Mode Function Active Mode Sleep Mode Subsleep Mode Standby Mode System clock oscillator Functioning Functioning Halted Halted Instructions Functioning Halted Halted Halted CPU operations Registers Functioning Retained Retained Retained RAM Functioning Retained Retained Retained IO ports Functioning Retained Retained Register contents are retained, but output is the high-impedance state. IRQ3, IRQ0 Functioning Functioning Functioning Functioning External interrupts WKP5 to WKP0 Functioning Functioning Functioning Functioning Timer V Functioning Functioning Reset Reset Peripheral functions Timer W Functioning Functioning Retained Retained (if internal clock φ is selected as a count clock, the counter is incremented by a subclock) Watchdog timer Functioning Functioning Retained Retained (functioning if the internal oscillator is selected as a count clock) SCI3 Functioning Functioning Reset Reset A/D converter Functioning Functioning Reset Reset |
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