HD64F36024 datasheet(11/384 Pages) RENESAS

11 / 384 page

Rev. 4.00 Sep. 23, 2005 Page xi of xxvi

6.2.2

Standby Mode ......................................................................................................... 75

6.2.3

Subsleep Mode........................................................................................................ 75

6.3

Operating Frequency in Active Mode.................................................................................. 76

6.4

Direct Transition .................................................................................................................. 76

6.5

Module Standby Function.................................................................................................... 76

Section 7 ROM ....................................................................................................77

7.1

Block Configuration.............................................................................................................78

7.2

Register Descriptions ...........................................................................................................79

7.2.1

Flash Memory Control Register 1 (FLMCR1)........................................................ 79

7.2.2

Flash Memory Control Register 2 (FLMCR2)........................................................ 80

7.2.3

Erase Block Register 1 (EBR1) .............................................................................. 81

7.2.4

Flash Memory Enable Register (FENR) ................................................................. 81

7.3

On-Board Programming Modes........................................................................................... 82

7.3.1

Boot Mode .............................................................................................................. 82

7.3.2

Programming/Erasing in User Program Mode........................................................ 85

7.4

Flash Memory Programming/Erasing .................................................................................. 86

7.4.1

Program/Program-Verify ........................................................................................ 86

7.4.2

Erase/Erase-Verify.................................................................................................. 88

7.4.3

Interrupt Handling when Programming/Erasing Flash Memory............................. 89

7.5

Program/Erase Protection .................................................................................................... 91

7.5.1

Hardware Protection ............................................................................................... 91

7.5.2

Software Protection................................................................................................. 91

7.5.3

Error Protection....................................................................................................... 91

Section 8 RAM ....................................................................................................93

Section 9 I/O Ports ...............................................................................................95

9.1

Port 1.................................................................................................................................... 95

9.1.1

Port Mode Register 1 (PMR1) ................................................................................ 96

9.1.2

Port Control Register 1 (PCR1) .............................................................................. 97

9.1.3

Port Data Register 1 (PDR1)................................................................................... 97

9.1.4

Port Pull-Up Control Register 1 (PUCR1).............................................................. 98

9.1.5

Pin Functions .......................................................................................................... 98

9.2

Port 2.................................................................................................................................. 100

9.2.1

Port Control Register 2 (PCR2) ............................................................................ 100

9.2.2

Port Data Register 2 (PDR2)................................................................................. 101

9.2.3

Pin Functions ........................................................................................................ 101

9.3

Port 5.................................................................................................................................. 102

9.3.1

Port Mode Register 5 (PMR5) .............................................................................. 103

HD64F36024 Datasheet(PDF) 11 Page - Renesas Technology Corp

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