HD64F36024 datasheet(93/384 Pages) RENESAS

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Section 5 Clock Pulse Generators

Rev. 4.00 Sep. 23, 2005 Page 67 of 354

REJ09B0025-0400

5.1.3

External Clock Input Method

Connect an external clock signal to pin OSC

1, and leave pin OSC2 open. Figure 5.6 shows a typical

connection. The duty cycle of the external clock signal must be 45 to 55%.

OSC1

External clock input

OSC 2

Open

Figure 5.6 Example of External Clock Input

5.2

Prescalers

5.2.1

Prescaler S

Prescaler S is a 13-bit counter using the system clock (

φ) as its input clock. It is incremented once

per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from

the reset state. In standby mode and subsleep mode, the system clock pulse generator stops.

Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S.

The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be

set separately for each on-chip peripheral function. In active mode and sleep mode, the clock input

to prescaler S is determined by the division factor designated by MA2 to MA0 in SYSCR2.

5.3

Usage Notes

5.3.1

Note on Resonators

Resonator characteristics are closely related to board design and should be carefully evaluated by

the user, referring to the examples shown in this section. Resonator circuit constants will differ

depending on the resonator element, stray capacitance in its interconnecting circuit, and other

factors. Suitable constants should be determined in consultation with the resonator element

manufacturer. Design the circuit so that the resonator element never receives voltages exceeding

its maximum rating.

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