HD64F36024 datasheet(72/384 Pages) RENESAS

72 / 384 page

Section 3 Exception Handling

Rev. 4.00 Sep. 23, 2005 Page 46 of 354

REJ09B0025-0400

Relative Module

Exception Sources

Vector Number Vector Address

Priority

CPU

Direct transition by executing

the SLEEP instruction

H'001A to H'001B

High

External interrupt

IRQ0

Low-voltage detection

interrupt*

H'001C to H'001D

IRQ3

H'0022 to H'0023

WKP

H'0024 to H'0025



Reserved for system use

H’0028 to H’0029

Timer W

Timer W input capture A

/compare match A

Timer W input capture B

/compare match B

Timer W input capture C

/compare match C

Timer W input capture D

/compare match D

Timer W overflow

H’002A to H’002B

Timer V

Timer V compare match A

Timer V compare match B

Timer V overflow

H'002C to H'002D

SCI3

SCI3 receive data full

SCI3 transmit data empty

SCI3 transmit end

SCI3 receive error

H'002E to H'002F

A/D converter

A/D conversion end

H'0032 to H'0033

SCI3_2

SCI3_2 receive data full

SCI3_2 transmit data empty

SCI3_2 transmit end

SCI3_2 receive error

H'0040 to H'0041

SCI3_3*

SCI3_3 receive data full

SCI3_3 transmit data empty

SCI3_3 transmit end

SCI3_3 receive error

H'0044 to H'0045

Low

Notes: 1. A low-voltage detection interrupt is enabled only in the product with an on-chip power-

on reset and low-voltage detection circuit.

2. The SCI3_3 function is incorporated in the H8/36024.

HD64F36024 Datasheet(PDF) 72 Page - Renesas Technology Corp

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