HD64F36024 datasheet(87/384 Pages) RENESAS

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Section 4 Address Break

Rev. 4.00 Sep. 23, 2005 Page 61 of 354

REJ09B0025-0400

When an address break is set in the data read cycle or data write cycle, the data bus used will

depend on the combination of the byte/word access and address. Table 4.1 shows the access and

data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a

byte access is generated twice. For details on data widths of each register, see section 17.1,

Table 4.1

Access and Data Bus Used

Word Access

Byte Access

Even Address Odd Address

ROM space

Upper 8 bits

Lower 8 bits

Upper 8 bits

RAM space

Upper 8 bits

Lower 8 bits

Upper 8 bits

I/O register with 8-bit data bus

width

Upper 8 bits

I/O register with 16-bit data

bus width

Upper 8 bits

Lower 8 bits

—

4.1.2

Address Break Status Register (ABRKSR)

ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.

Bit

Bit Name

Initial

Value

R/W

Description

ABIF

R/W

Address Break Interrupt Flag

[Setting condition]

When the condition set in ABRKCR is satisfied

[Clearing condition]

When 0 is written after ABIF=1 is read

ABIE

R/W

Address Break Interrupt Enable

When this bit is 1, an address break interrupt request is

enabled.

5 to 0

—

All 1

—

Reserved

These bits are always read as 1.

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