HD64F36024 datasheet(76/384 Pages) RENESAS

Part #	HD64F36024

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

PDF	384 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 3 Exception Handling

Rev. 4.00 Sep. 23, 2005 Page 50 of 354

REJ09B0025-0400

3.2.4

Interrupt Flag Register 1 (IRR1)

IRR1 is a status flag register for direct transition interrupts, and

IRQ3 and IRQ0 interrupt requests.

Bit

Bit Name

Initial

Value

R/W

Description

IRRDT

R/W

Direct Transfer Interrupt Request Flag

[Setting condition]

When a direct transfer is made by executing a SLEEP

instruction while DTON in SYSCR2 is set to 1.

[Clearing condition]

When IRRDT is cleared by writing 0



Reserved

This bit is always read as 0.

5, 4



All 1



Reserved

These bits are always read as 1.

IRRI3

R/W

IRQ3 Interrupt Request Flag

[Setting condition]

When

IRQ3 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IRRI3 is cleared by writing 0

2, 1



All 0



Reserved

These bits are always read as 0.

IRRl0

R/W

IRQ0 Interrupt Request Flag

[Setting condition]

When

IRQ0 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IRRI0 is cleared by writing 0

HD64F36024 Datasheet(PDF) 76 Page - Renesas Technology Corp

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