HD64F36024 datasheet(96/384 Pages) RENESAS

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Section 6 Power-Down Modes

Rev. 4.00 Sep. 23, 2005 Page 70 of 354

REJ09B0025-0400

6.1.1

System Control Register 1 (SYSCR1)

SYSCR1 controls the power-down modes, as well as SYSCR2.

Bit

Bit Name

Initial

Value

R/W

Description

SSBY

R/W

Software Standby

This bit selects the mode to transit after the execution of

the SLEEP instruction.

0: a transition is made to sleep mode

1: a transition is made to standby mode.

For details, see table 6.2.

STS2

STS1

STS0

R/W

Standby Timer Select 2 to 0

These bits designate the time the CPU and peripheral

modules wait for stable clock operation after exiting from

standby mode, to active mode or sleep mode due to an

interrupt. The designation should be made according to

the clock frequency so that the waiting time is at least 6.5

ms. The relationship between the specified value and the

number of wait states is shown in table 6.1. When an

external clock is to be used, the minimum value (STS2 =

STS1 = STS0 =1) is recommended.

3 to 0



All 0



Reserved

These bits are always read as 0.

Table 6.1

Operating Frequency and Waiting Time

Bit Name

Operating Frequency

STS2

STS1 STS0 Waiting Time

20 MHz

16 MHz

10 MHz

8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz

8,192 states

0.4

0.5

0.8

1.0

2.0

4.1

8.1

16.4

16,384 states

0.8

1.0

1.6

2.0

4.1

8.2

16.4

32.8

32,768 states

1.6

2.0

3.3

4.1

8.2

16.4

32.8

65.5

65,536 states

3.3

4.1

6.6

8.2

16.4

32.8

65.5

131.1

131,072 states

6.6

8.2

13.1

16.4

32.8

65.5

131.1

262.1

1,024 states

0.05

0.06

0.10

0.13

0.26

0.51

1.02

2.05

128 states

0.00

0.01

0.02

0.03

0.06

0.13

0.26

16 states

0.00

0.01

0.02

0.03

Note:

Time unit is ms.

HD64F36024 Datasheet(PDF) 96 Page - Renesas Technology Corp

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