AFE8405 datasheet(37/152 Pages) TI

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7.1.4

Test and Noise Signal Generator

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

www.ti.com

SLWS212 – OCTOBER 2008

PROGRAMMING

VARIABLE

DESCRIPTION

ssel_ragc_clear_X(2:0)

Sync source selection for the AGC loop accumulator clear

ragc_freeze_X

ragc_clear_X

ragc_update_X(7:0)

Sets the number of updates per sync event, after which no further updates occur until the next sync

event. Program to 0x00 to update continually.

sd_ena_X

Enables freezing the AGC with the signal detector when set

sd_thresh_X(15:0)

Signal-detection threshold for AGC channel X. This 16-bit word is lined up with bits 23 down to 8 of the

square output. The smallest signal level that can be programmed is therefore 16 LSBs on the ADC

input, and the largest is 4095 LSBs at the ADC input.

sd_samples_X(15:0)

The number of samples below the signal detect threshold within the signal detect sample timer window

required to freeze on the AGC.

sd _timer_X(15:0)

Window timer to qualify signal detection.

clip_hi_thresh_X(15:0)

Clip detector high threshold

clip_lo_thresh_X(15:0)

Clip detector low threshold

clip_hi_samples_X(7:0)

A clip event is detected when the number of samples above the clip-high threshold within the clip-high

sample timer window exceeds this value.

clip_lo_samples_X(7:0)

A clip event ends when the number of samples below the clip-low threshold within the clip-low sample

timer window exceeds this value.

clip_hi_timer_X(15:0)

Window timer to qualify clip events

clip_lo_timer_X(15:0)

Window timer to determine when the clip event ends.

clip_error_X(15:0)

Error signal applied to the AGC accumulator when a clip event is active. This data is MSB aligned, and

therefore can cause immediate changes to the accumulator.

ragc_error_map_X

128-word

× 8-bit memory holding the log to error look up table

dvga_map_X

64-word

× 6-bit memory holding the accumulator to DVGA look-up table

gain_map_X

64-word

× 16-bit memory holding the accumulator to GAIN look-up table (256 decibels is unity gain).

delay_adj_X(4:0)

Delay between DVGA output updates and gain map updates to compensate for ADC pipeline delays,

etc.

err_shift_X(4:0)

Error map table shift-up output before adding to loop accumulator

complex_01

Enables complex AGC mode on inputs rxin_a and rxin_b when set

complex_23

Enables complex AGC mode on inputs rxin_c and rxin_d when set

ragc_accum_X(31:0)

32-bit read-only register holding the current contents of the loop accumulator.

3-state(10:7)

3-state controls for the dvga_d/c/b/a output pins; pins are in the high-impedance state when the 3-state

bits are set.

ragc_mpu_ram_read

When set, the receive AGC map RAMs are readable via the MPU control interface. The AFE8405 signal

path is not operational when this bit is set, it is intended for debug purposes only.

The test and noise generator can generate test signals to replace the rxin_a/b/c/d inputs as a tool for

debug, evaluation, and self-test. Checksum generators included in the individual DDC channels at the

outputs can be used in conjunction with the noise generator and the internal sync timer block to create the

built-in self-test function.

The test and noise signal source included in this block is a 23-bit linear feedback shift register (LFSR) with

a fixed polynomial and fixed initialization state. A sync input is required to initialize the LFSR, and the sync

source is connected to the ddc_counter output signal.

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