AFE8405 datasheet(85/152 Pages) TI

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8.4.2.4 GBL_PAR_CONFIG0 Register

8.4.2.5 GBL_PAR_CONFIG1 Register

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

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SLWS212 – OCTOBER 2008

Address: 0x03

BIT 15

BIT 8

par_recv_sync_del(6:0)

tst_clk_pol

BIT 7

BIT 0

par_recv_clkdiv(6:0)

par_recv_

rxclk_pol

par_recv_sync_del(6:0): Delays the sync source from the DDC0 AGC output by (par_recv_sync_del+1)

rxclk cycles.

tst_clk_pol: Selects the polarity of the test clock output at dvga_c(1) when the test bus is enabled; 0 for

rising edge in the center of valid data, 1 for falling edge in the center of valid data. No effect

when tst_rate_sel is 0 0000.

par_recv_clkdiv(6:0): Selects the parallel interface output clock rate.

par_recv_rxclk_pol: Selects the polarity of the rxclk_out clock output; 0 for rising edge in the center of

valid data, 1 for falling edge in the center of valid data.

Address: 0x04

BIT 15

BIT 8

par_recv_syncout_del(3:0)

par_recv_chan(3:0)

BIT 7

BIT 0

par_recv_fsinvl(6:0)

par_recv_

sync_pol

par_recv_syncout_del(3:0): Changes the rx_sync_out position with respect to IQ DDC0. Setting to 0

causes rx_sync_out to lead IQ DDC0 by 1 output sample, setting to 1 causes rx_sync_out to

line up with IQ DDC0, setting to 2 causes rx_sync_out to trail IQ DDC0 by 1 output sample,

etc.

par_recv_chan(3:0): Selects the number of channels to be output over the parallel interface, from 1 to 16

channels.

par_recv_fsinvl(6:0): Selects the number of rxclk cycles per parallel interface frame, from 1 to 128

cycles.

par_recv_sync_pol: Selects the polarity of the parallel interface sync pulse; 0 for active-low, 1 for

active-high.

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