AFE8405 datasheet(24/152 Pages) TI

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ANALOG-TO-DIGITAL CONVERTERS

B0105-02

refpa

refma

Internal

Reference

S&H

14-Bit

Pipelined

ADCCore

Dual14-Bit85-MSPS ADC

Digital

Error

Correction

Output

Control

TimingCircuitry

inpa

inma

clkpa

clkma

da(13:0)

ovra

clkouta

6.1 ADC Operation

6.2 ADC Input Configuration

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

SLWS212 – OCTOBER 2008

www.ti.com

The AFE8405 includes a high-performance, single-channel, 14-bit, 85-MSPS analog-to-digital converter

(ADC). To provide a complete solution, the

ADC

channel

includes

high-bandwidth

linear

sample-and-hold stage (S&H) and internal reference. An internal reference is provided, simplifying system

design requirements, yet an external reference can be used optionally to suit the accuracy and low-drift

requirements of the application.

Figure 6-1. ADC Block Diagram

The ADC digital output data and output clocks are connected directly to the rxin_a port of the AFE8405

digital section. The ovra output connects directly to the AFE8405 digital section and also to a package

ball. The ADC outputs can be accessed through the test bus in decimate-by-32

× mode only.

The conversion process is initiated by a falling edge of the external input clocks. Once the signal is

captured by the input S&H, the input sample is sequentially converted by a series of small resolution

stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock

edges are used to propagate the sample through the pipeline every half clock cycle. This process results

in data latency of 16.5 clock cycles, after which the output data is available as a 14-bit parallel word,

coded in binary 2s-complement format to the AFE8405 receive section.

The analog input for the ADC consists of a differential sample-and-hold architecture implemented using a

switched-capacitor technique shown in Figure 6-2.

ANALOG-TO-DIGITAL CONVERTERS

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