AFE8405 datasheet(49/152 Pages) TI

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7.2.4

DDC Filtering and Decimation

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

www.ti.com

SLWS212 – OCTOBER 2008

Each of the 16 CDMA DDC channels can be loaded with unique frequency values.

The phase of the NCO sin/cos output can be adjusted relative to the phase of other channel NCOs by

specifying a phase offset. The phase offset is programmed as a 16-bit word, yielding a step size of about

5.5 m

°. The phase offset word is determined by the formula:

Phase offset word = 216

× offset_in_degrees / 360, or

Phase offset word = 216

× offset_in_radians / 2π

PHASE PROGRAMMING

VARIABLE

DESCRIPTION

phase_offset_a(15:0)

16-bit phase offset word for the A-side DDC when in CDMA mode. Also for UMTS mode.

phase_offset_b(15:0)

16-bit phase offset word for the B-side DDC when in CDMA mode. Not used in UMTS mode.

Each of the 16 CDMA DDC channels can be loaded with unique phase-offset values.

Various synchronization signals are available which are used to synchronize the NCOs of all channels

with respect to each other. Frequency sync and phase-offset sync determine when frequency and phase

offset changes occur. For example, generating a frequency sync after programming the two frequency

words causes the NCO (or multiple NCOs) to change frequency at that time, rather than after each of the

three frequency words is programmed over the control bus. The zero-phase sync signal is used to force

the sine and cosine oscillators to their zero-phase state. Dither sync can be used to synchronize the dither

generators of multiple NCOs. The NCOs used in the transmit section are identical to what is described for

the receive section. Note that there is one set of syncs provided for each DDC. When one DDC is used to

process two CDMA signals, the syncs are shared between them.

SYNC PROGRAMMING

VARIABLE

DESCRIPTION

ssel_nco(2:0)

Sync source for NCO accumulator reset

ssel_dither(2:0)

Sync source for NCO dither reset

ssel_freq(2:0)

Sync source for NCO frequency register loading

ssel_phase(2:0)

Sync source for NCO phase register loading

The purpose of the receive filter chain is to isolate the signal of interest (and reject all others) that has

been previously translated to baseband via the mixer and NCO. The overall decimation through the chain

must be considered. The goal, generally, is to output the isolated signal at a rate that is twice (2

×) the

signal’s chip rate. For UMTS this would be 7.68 MSPS and for CDMA the output rate should be 2.4576

MSPS. TD-SCDMA systems require the output rate be the chip rate of 1.28 MSPS. The output interface is

programmed to decimate by 2 for the TD-SCDMA case.

Receive filtering and decimation is performed in several stages:

1. Zero-padding to interpolate the input sample rate (if needed) up to the rxclk rate

2. High-rate decimation (4 to 32) using a six-stage cascade-integrate-comb filter (CIC)

3. Decimate-by-two compensation filtering using the programmable compensating FIR filter (CFIR)

4. Pulse-shape filtering via the programmable FIR filter (PFIR) with no decimation

5. Output interface, serial or parallel format, with no decimation or decimate-by-2

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