AFE8405 datasheet(76/152 Pages) TI

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8.2 Synchronization Signals

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

SLWS212 – OCTOBER 2008

www.ti.com

Various function blocks within the AFE8405 must be synchronized in order to realize predictable results.

The AFE8405 provides a flexible system where each function block that requires synchronization can be

independently synchronized from either device pins or from a software one-shot. The one-shot option is

setup and triggered through control registers. The four sync input pins, rxsync_a, rxsync_b, rxsync_c and

rxsync_d are qualified on the rxclk rising clock edge. Table 8-1 shows the different sync modes available.

Table 8-1. Different Sync Modes Available

SYNC SELECT CODE

RECEIVE SYNC SOURCE

000

rxsync_a

001

rxsync_b

010

rxsync_c

011

rxsync_d

100

ddc sync counter terminal count

101

ddc sync triggered by software one-shot (register bit)

110

0 (always off)

111

1 (always on)

Table 8-2 and Table 8-3 summarizes the blocks which have functions that can be synchronized using the

eight sync source options listed in Table 8-1.

Table 8-2. Receive Common Syncs

Sync Name

Purpose

sync_ddc_counter

Initializes the receive sync counter

sync_ddc

Initializes the receive ADC interface and clock generation circuits

sync_rxsync_out

Selects sync signal to be output on the rx_sync_out pin.

sync_adc_fifo

Initializes the input and output pointers in the ADC fifo circuits.

sync_tst_decim

Initializes the testbus decimation counter.

sync_recv_pmeterX

Initializes the rxin power meters. {X = 0, 1, 2, or 3}

sync_ragc_interval_X

Initializes the rxin receive AGC timers. {X = 0, 1, 2, or 3}

sync_ragc_freeze_X

rxin receive AGC freeze mode control. {X = 0, 1, 2, or 3}

sync_ragc_clear_X

Initializes the receive AGC error accumulator. {X = 0, 1, 2, or 3}

Table 8-3. DDC Channel Syncs

Sync Name

Purpose

sync_ddc_tadj

Selects zero stuff moment in the tadj fine-adjustment section

sync_ddc_tadj_reg

Updates the tadj output pointer register delay in the tadj coarse-adjustment section

sync_ddc_nco

Resets the NCO accumulator

sync_ddc_freq

Updates the NCO freq registers

sync_ddc_phase

Updates the NCO phase register

sync_ddc_dither

Initializes the NCO dither circuits

sync_ddc_cic

Selects the CIC decimation moment

sync_ddc_pmeter

Initializes the receive channel power meters

sync_ddc_gain

Updates the DDC channel AGC gain registers

sync_ddc_agc

Initializes the AGC accumulator

sync_ddc_agc_freeze

AGC freeze mode control

sync_ddc_serial

Initializes the receive serial interface

AFE8405 GENERAL CONTROL

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