AFE8405 datasheet(69/152 Pages) TI

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T0117-01

rxclk

rxsync_out_X

MSB

rxsync_X

ProgrammedBit Time

(2rxclkCyclesfor ThisExample)

tsetup

thold

tpd

rxout_X_Y

rxsync_XCanbeaPulseorLevel-InterfaceWillGeneratePeriodicFrameStrobesUsingProgrammedFrameSyncInterval

3rxclk+1ProgrammedBit Time

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

www.ti.com

SLWS212 – OCTOBER 2008

Four serial pins each for I and Q data can be optionally employed (instead of two for I and two for Q) at

half the output rate. This would most likely be used when two DDC channels (2k and 2k + 1, k = 0 to 5)

are combined to support double-length PFIR filtering (a channel is sacrificed). Formatting for I data is then:

Imsb, Imsb-1, Imsb-2, Imsb-3. Q data formatting is: Qmsb, Qmsb-1, Qmsb-2, Qmsb-3.

The frame strobe signal provided on the rx_sync_out_X pins can be programmed to arrive from 0 to 3 bit

clocks early via a 2-bit control parameter. The frame interval can be programmed from 1 to 63 bits. A

programmable 4-bit clock divider circuit is used to specify the serial bit rate. The clock divider circuit is

synchronized using a sync block discussed later in this document.

Programming the serial port clock divider requires some thought and depends upon the channel's overall

decimation ratio, frame sync interval, number of output bits, and CDMA-UMTS mode.

In general:

the serial clock divide ratio

the frame sync interval = the total receive decimation

The relationship between the number of serial bits output, clock divide ratio, and overall decimation ratio

is:

CDMA: [overall decimation

(pser_recv_8pin + 1) ] / (pser_recv_clkdiv + 1)

≥ pser_recv_bits + 1

UMTS: 2

[overall decimation

(pser_recv_8pin + 1) ] / (pser_recv_clkdiv + 1)

≥ pser_recv_bits + 1

where overall decimation = CIC DECIMATION

× CFIR DECIMATION.

Decimation by 2 in the output interface can be achieved by setting the frame strobe interval and clock

divider to 1/2 the PFIR output rate. The serial interface samples the PFIR output each time the transfer

interval defined by these two settings has completed. The decimation moment can be controlled using the

rxsync_X input signal selected as the sync source for the serial interface.

The timing diagram in Figure 7-31 shows the DDC serial output timing.

Figure 7-31. Serial Output Interface Timing Diagram

PROGRAMMING

VARIABLE

DESCRIPTION

pser_recv_fsinvl(6:0)

Frame sync interval in bits

pser_recv_bits(4:0)

Number of data output bits – 1. e.g., 10001 = 18 bits

pser_recv_clkdiv(3:0)

Receive serial interface clock divider rate – 1.

0 = rcclk, 15 = rxclk/16

pser_recv_8pin

When set, configures the serial out pins for 4I and 4Q in UMTS mode. When cleared, the mode is 2I

and 2Q. Used in conjunction with pser_recv_alt.

pser_recv_alt

When set, outputs Q data from adjacent DDC channel.

pser_recv_fsdel(1:0)

Number of bit clocks the frame sync is output early with respect to serial data.

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